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The MOSFET gain stage in Figure 5-75 (p. 254) has the following parameters: NMOS                          PMOS Vtn = 0.7V                     Vtp = -0.8V VGS2 = ?                        VGS1 = -1.5V kn = 185 uA/V2             kp = 292 uA/V2 (a) Determine gm for each transistor. (b) Determine the voltage gain.

The MOSFET gain stage in Figure 5-75 (p. 254) has the following parameters: NMOS                          PMOS Vtn = 0.7V                     Vtp = -0.8V VGS2 = ?                        VGS1 = -1.5V kn = 185 uA/V2             kp = 292 uA/V2 (a) Determine gm for each transistor. (b) Determine the voltage gain.

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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The MOSFET gain stage in Figure 5-75 (p. 254) has the following parameters:

NMOS                          PMOS

Vtn = 0.7V                     Vtp = -0.8V

VGS2 = ?                        VGS1 = -1.5V

kn = 185 uA/V2             kp = 292 uA/V2

(a) Determine gm for each transistor. (b) Determine the voltage gain.

### Figure 5-75: NMOS Inverter Circuit This diagram illustrates a basic NMOS inverter circuit used in digital electronics for switching applications. The circuit consists of two NMOS transistors, labeled \( M_1 \) and \( M_2 \), arranged in a complementary fashion. **Components and Connections:** - **Transistors**: - \( M_1 \) is connected to a +5 V power supply, while \( M_2 \) is connected to a -5 V supply. - The gates of both transistors receive control voltages \( V_{\text{GS1}} \) and \( V_{\text{GS2}} \), respectively. - **Resistor**: - A 600-ohm resistor is placed in series with the input voltage source, providing the necessary bias to the gate of transistor \( M_1 \). - **Voltage Source**: - The input voltage is applied through a signal generator symbolized by a circle with a sinusoidal waveform, indicating an AC input. - **Output**: - The output voltage, \( V_{\text{out}} \), is measured at the common connection between the two transistors' drains. This circuit serves a critical function in digital logic as it allows the output to switch states based on the input voltage, typically used in logic gates for computing operations. *Exercise 5-24* in the referenced educational material likely involves analyzing this circuit's behavior under various input conditions or determining the characteristic parameters of its operation.
Transcribed Image Text:### Figure 5-75: NMOS Inverter Circuit This diagram illustrates a basic NMOS inverter circuit used in digital electronics for switching applications. The circuit consists of two NMOS transistors, labeled \( M_1 \) and \( M_2 \), arranged in a complementary fashion. **Components and Connections:** - **Transistors**: - \( M_1 \) is connected to a +5 V power supply, while \( M_2 \) is connected to a -5 V supply. - The gates of both transistors receive control voltages \( V_{\text{GS1}} \) and \( V_{\text{GS2}} \), respectively. - **Resistor**: - A 600-ohm resistor is placed in series with the input voltage source, providing the necessary bias to the gate of transistor \( M_1 \). - **Voltage Source**: - The input voltage is applied through a signal generator symbolized by a circle with a sinusoidal waveform, indicating an AC input. - **Output**: - The output voltage, \( V_{\text{out}} \), is measured at the common connection between the two transistors' drains. This circuit serves a critical function in digital logic as it allows the output to switch states based on the input voltage, typically used in logic gates for computing operations. *Exercise 5-24* in the referenced educational material likely involves analyzing this circuit's behavior under various input conditions or determining the characteristic parameters of its operation.
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