The following system is designed such that it outputs the average of the most recent two data input samples. The system has an 8-bit unsigned data input I and an 8-bit unsigned output. The data input is sampled when a single bit input S changes from 0 to 1. Fill in the blanks and of the diagram with appropriate S input (Note: Please enter the answer as S or S', nothing else would be accepted as answer.) Inputs: I (8 bits), S (bit) Outputs: avg (8 bits) Local Registers: Prevreg (8 bits), Ireg (8 bits), avgreg (8 bits) A Init Prevreg: 0 Ireg: 0 avgreg: 0 B Wait D E Prevreg :- Ireg Ireg := I avgreg:= (Prevreg +Ireg)/2 Sample WaitLow

The following system is designed such that it outputs the average of the most recent two data input samples. The system has an 8-bit unsigned data input I and an 8-bit unsigned output. The data input is sampled when a single bit input S changes from 0 to 1. Fill in the blanks and of the diagram with appropriate S input (Note: Please enter the answer as S or S', nothing else would be accepted as answer.) Inputs: I (8 bits), S (bit) Outputs: avg (8 bits) Local Registers: Prevreg (8 bits), Ireg (8 bits), avgreg (8 bits) A Init Prevreg: 0 Ireg: 0 avgreg: 0 B Wait D E Prevreg :- Ireg Ireg := I avgreg:= (Prevreg +Ireg)/2 Sample WaitLow

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Question

The following system is designed such that it outputs the average of the most recent
two data input samples. The system has an 8-bit unsigned data input I and an 8-bit
unsigned output. The data input is sampled when a single bit input S changes from 0
to 1.
Fill in the blanks
and
of the diagram with
appropriate S input (Note: Please enter the answer as S or S', nothing else would be
accepted as answer.)
Inputs: I (8 bits), S (bit)
Outputs: avg (8 bits)
Local Registers: Prevreg (8 bits), Ireg (8 bits),
avgreg (8 bits)
A
Init
Prevreg :- 0
Ireg: 0
avgreg: 0
B
Wait
E
Prevreg :- Ireg
Ireg := I
avgreg:=
(Prevreg + Ireg)/2
Sample
WaitLow

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