The following instructions are in the pipeline from newest to oldest: beq, addi, add, Iw, sw. Which pipeline register(s) have RegWrite true? More than option can be correct. Select and explain all the correct answers. 1. PC 2. IF/ID 3. ID/EX 7. EX/MEM 5. MEM/WB Address Add Instruction memory Read reguler Read reger 2 Wite dala Control Wite Registers Read data 2 register Instruction (15-0 Read data Sign 3 extend IDEX SN left 2 Ada As Tesun ALU ALUS Zero ALU ALLE resur EXMEM WE M Branch Address Write Data memory Read MEMWB

Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
The following instructions are in the pipeline from newest to oldest: beq, addi, add,
Iw, sw. Which pipeline register(s) have RegWrite == true? More than option can be
correct. Select and explain all the correct answers.
1. PC
2. IF/ID
3. ID/EX
4.
5.
EX/MEM
MEM/WB
LOD
PC Address
Add
Instruction
memory
IF: beq
IFAD
Instruction
Read
register 1
Read
register 2
RegWrite
Write
register
Write
data
Instruction
[15-0]
Control
Registers Read
data 2
ID:
addi
Read
data 1
Sign- 32
extend
ID/EX
WB
Shift
left 2
Add
Addesult
ALUSrc
ALU ALU
result
ALU
control
EX:
ZeraH+
add
nagust
EX/MEM
Branch
MemWrite
Address
Write
data
Data
memory
Read
data
MemRead
MEM:
Iw
MEM/WB
WB:
SW
Transcribed Image Text:The following instructions are in the pipeline from newest to oldest: beq, addi, add, Iw, sw. Which pipeline register(s) have RegWrite == true? More than option can be correct. Select and explain all the correct answers. 1. PC 2. IF/ID 3. ID/EX 4. 5. EX/MEM MEM/WB LOD PC Address Add Instruction memory IF: beq IFAD Instruction Read register 1 Read register 2 RegWrite Write register Write data Instruction [15-0] Control Registers Read data 2 ID: addi Read data 1 Sign- 32 extend ID/EX WB Shift left 2 Add Addesult ALUSrc ALU ALU result ALU control EX: ZeraH+ add nagust EX/MEM Branch MemWrite Address Write data Data memory Read data MemRead MEM: Iw MEM/WB WB: SW
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