The current mirror is supposed to faithfully reproduce the input current at its output, but even if the two transistors are designed identically, the Early effect causes problems. Using the circuit in figure below and parameter values from prelab problem #2, estimate the drain voltage of M1. VDD 10K R M1 M2 NEET current mirror Prelab problem2: R1 R3 4.7K 20K Vo R4 R2 10K 470 Assuming VDD-+5V and VSS=-5V, calculate the DC bias conditions for the common-source (and also common-drain) amplifier shown in Figure. Determine VG, VS, VD and ID. For this calculation, assume that Vt = 1.2 and that kn *(W/ L) 300 μ Α/V2 %3D

Introductory Circuit Analysis (13th Edition)
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The current mirror is supposed to faithfully reproduce the input current at its
output, but even if the two transistors are designed identically, the Early effect
causes problems. Using the circuit in figure below and parameter values from
prelab problem #2, estimate the drain voltage of M1.
VDD
VDD
10K
R
M1
M2
DFET current mirror
Prelab problem2:
R1
R3
4.7K
20K
Vo
R4
R2
10K
470
Assuming VDD=+5V and VSS= -5V, calculate the DC bias conditions for the
common-source (and also common-drain) amplifier shown in Figure. Determine
VG, VS, VD and ID. For this calculation, assume that Vt = 1.2 and that kn '(W/ L)
=300 μ ΑV2
Transcribed Image Text:The current mirror is supposed to faithfully reproduce the input current at its output, but even if the two transistors are designed identically, the Early effect causes problems. Using the circuit in figure below and parameter values from prelab problem #2, estimate the drain voltage of M1. VDD VDD 10K R M1 M2 DFET current mirror Prelab problem2: R1 R3 4.7K 20K Vo R4 R2 10K 470 Assuming VDD=+5V and VSS= -5V, calculate the DC bias conditions for the common-source (and also common-drain) amplifier shown in Figure. Determine VG, VS, VD and ID. For this calculation, assume that Vt = 1.2 and that kn '(W/ L) =300 μ ΑV2
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