Task 2: DESIGN A 4-TO-1 LINE MULTIPLEXER BY USING THREE 2-TO-1 MUXS. CONSIDER THAT INPUTS ARE I3,12,11,10 AND SELECTIVE LINES si,so ,GIVEN ACCORDING TO DEXCENDING SIGNIFICANCE ORDER. A) Write truth table. (Condensed version) B) Draw the logic diagram. (You can use the 2:1 MUX blocks or you can draw the circuit by using NAND & NOT GATES.) c) Simulate the circuit by using NAND & NOT GATES. Io (2:1 MUx BLOCK)
Task 2: DESIGN A 4-TO-1 LINE MULTIPLEXER BY USING THREE 2-TO-1 MUXS. CONSIDER THAT INPUTS ARE I3,12,11,10 AND SELECTIVE LINES si,so ,GIVEN ACCORDING TO DEXCENDING SIGNIFICANCE ORDER. A) Write truth table. (Condensed version) B) Draw the logic diagram. (You can use the 2:1 MUX blocks or you can draw the circuit by using NAND & NOT GATES.) c) Simulate the circuit by using NAND & NOT GATES. Io (2:1 MUx BLOCK)
Chapter22: Sequence Control
Section: Chapter Questions
Problem 6SQ: Draw a symbol for a solid-state logic element AND.
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![Task 2: DESIGN A 4-T0-1 LINE MULTIPLEXER BY USING THREE 2-TO-1 MUXS.
CONSIDER THAT INPUTS ARE I3,12,11,10 AND SELECTIVE LINES S1,so
,GIVEN ACCORDING TO DEXCENDING SIGNIFICANCE ORDER.
A) Write truth table. (Condensed version)
B) Draw the logic diagram. (You can use the 2:1 MUX blocks or
you can draw the circuit by using NAND & NOT GATES.)
C) Simulate the circuit by using NAND & NOT GATES.
Io
Il
(2:1 MUx BLOCK)](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F6af1a739-1430-4de1-b33d-f92576a4e279%2F135e1ca6-93b0-4b95-b419-2f7c560d5b41%2F4rse5l_processed.png&w=3840&q=75)
Transcribed Image Text:Task 2: DESIGN A 4-T0-1 LINE MULTIPLEXER BY USING THREE 2-TO-1 MUXS.
CONSIDER THAT INPUTS ARE I3,12,11,10 AND SELECTIVE LINES S1,so
,GIVEN ACCORDING TO DEXCENDING SIGNIFICANCE ORDER.
A) Write truth table. (Condensed version)
B) Draw the logic diagram. (You can use the 2:1 MUX blocks or
you can draw the circuit by using NAND & NOT GATES.)
C) Simulate the circuit by using NAND & NOT GATES.
Io
Il
(2:1 MUx BLOCK)
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