Table Q15 shows the micro-operations of fetch cycle, interrupt cycle, and execute cycle of the ADD instruction. Note: Accumulator (AC), internal registers (Y, Z), Interrupt Service Routine (ISR) TABLE Q15 Execute cycle of ADD instruction (i.e. ADD АС, Х) Clock cycle Fetch cycle Interrupt cycle T1 MAR PC MBR PC MAR Save address PC Memory MAR X MBR + T2 MBR Memory Memory PC – IR MBR ISR T3 MBR Y MBR T4 Z AC+ Y T5 AC Z Based on Table Q15, give the micro-operations of the execute cycle of the add instruction using the immediate addressing mode (i.e. ADIM AC, X). (a) (b) Give the micro-operations of the execute cycle of the add instruction using the indirect mode (i.e. ADIN AC, X).
Table Q15 shows the micro-operations of fetch cycle, interrupt cycle, and execute cycle of the ADD instruction. Note: Accumulator (AC), internal registers (Y, Z), Interrupt Service Routine (ISR) TABLE Q15 Execute cycle of ADD instruction (i.e. ADD АС, Х) Clock cycle Fetch cycle Interrupt cycle T1 MAR PC MBR PC MAR Save address PC Memory MAR X MBR + T2 MBR Memory Memory PC – IR MBR ISR T3 MBR Y MBR T4 Z AC+ Y T5 AC Z Based on Table Q15, give the micro-operations of the execute cycle of the add instruction using the immediate addressing mode (i.e. ADIM AC, X). (a) (b) Give the micro-operations of the execute cycle of the add instruction using the indirect mode (i.e. ADIN AC, X).
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
Transcribed Image Text:Table Q15 shows the micro-operations of fetch cycle, interrupt cycle, and execute
cycle of the ADD instruction.
Note: Accumulator (AC), internal registers (Y, Z), Interrupt Service Routine (ISR)
TABLE Q15
Execute cycle of ADD
instruction (i.e. ADD
АС, X)
MAR X
Clock
сycle
Fetch cycle
Interrupt cycle
T1
MAR PC
MBR - PC
MBR +
MAR
Save
T2
Memory PC
MBR – Memory
address PC ISR
Memory MBR
T3
IR - MBR
Y
MBR
T4
Z AC + Y
T5
AC Z
Based on Table Q15, give the micro-operations of the execute cycle of the
add instruction using the immediate addressing mode (i.e. ADIM AC, X).
(a)
(b)
Give the micro-operations of the execute cycle of the add instruction using
the indirect mode (i.e. ADIN AC, X).
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