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TABLE 9.1 The Characteristics of RISC Machines Versus CISC Machines RISC CISC Multiple register sets, often consisting of more than 256 registers Single register set, typically 6 to 16 registers total Three register operands allowed per instruction (e.g., add R1, R2, R3) One or two register operands allowed per instruction (e.g., add R1, R2) Parameter passing through efficient on-chip register windows Parameter passing through inefficient off-chip memory Single-cycle instructions (except for load and store Multiple-cycle instructions Hardwired control Microprogrammed control Highly pipelined Less pipelined Simple instructions that are few in number Many complex instructions Fixed-length instructions Variable-length instructions Complexity in compiler Complexity in microcode Only load and store instructions Many instructions can access can access memory memory

TABLE 9.1 The Characteristics of RISC Machines Versus CISC Machines RISC CISC Multiple register sets, often consisting of more than 256 registers Single register set, typically 6 to 16 registers total Three register operands allowed per instruction (e.g., add R1, R2, R3) One or two register operands allowed per instruction (e.g., add R1, R2) Parameter passing through efficient on-chip register windows Parameter passing through inefficient off-chip memory Single-cycle instructions (except for load and store Multiple-cycle instructions Hardwired control Microprogrammed control Highly pipelined Less pipelined Simple instructions that are few in number Many complex instructions Fixed-length instructions Variable-length instructions Complexity in compiler Complexity in microcode Only load and store instructions Many instructions can access can access memory memory

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Which characteristics of RISC systems could be directly implemented in CISC systems? Which characteristics of RISC machines could not be implemented in CISC machines (based on the defining characteristics of both architectures as listed in Table 9.1)?

TABLE 9.1 The Characteristics of RISC Machines Versus CISC Machines RISC CISC Multiple register sets, often consisting of more than 256 registers Single register set, typically 6 to 16 registers total Three register operands allowed per instruction (e.g., add R1, R2, R3) One or two register operands allowed per instruction (e.g., add R1, R2) Parameter passing through efficient on-chip register windows Parameter passing through inefficient off-chip memory Single-cycle instructions (except for load and store Multiple-cycle instructions Hardwired control Microprogrammed control Highly pipelined Less pipelined Simple instructions that are few in number Many complex instructions Fixed-length instructions Variable-length instructions Complexity in compiler Complexity in microcode Only load and store instructions Many instructions can access can access memory memory
Transcribed Image Text:TABLE 9.1 The Characteristics of RISC Machines Versus CISC Machines RISC CISC Multiple register sets, often consisting of more than 256 registers Single register set, typically 6 to 16 registers total Three register operands allowed per instruction (e.g., add R1, R2, R3) One or two register operands allowed per instruction (e.g., add R1, R2) Parameter passing through efficient on-chip register windows Parameter passing through inefficient off-chip memory Single-cycle instructions (except for load and store Multiple-cycle instructions Hardwired control Microprogrammed control Highly pipelined Less pipelined Simple instructions that are few in number Many complex instructions Fixed-length instructions Variable-length instructions Complexity in compiler Complexity in microcode Only load and store instructions Many instructions can access can access memory memory
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