Table 8.2 Verilog Operator Precedence +-!- & -&|- |-1l- (unary) Highest precedence */% +2 (binary) VW <<<>>> << =>>= == !==== ! == & (binary) (Bitwise, Reduction AND) M- -A (binary) (Bitwise, Reduction OR) | (binary) && (logical AND) | (logical OR) ?: (conditional operator) { }{{ }} (concatenation) Lowest precedence
Table 8.2 Verilog Operator Precedence +-!- & -&|- |-1l- (unary) Highest precedence */% +2 (binary) VW <<<>>> << =>>= == !==== ! == & (binary) (Bitwise, Reduction AND) M- -A (binary) (Bitwise, Reduction OR) | (binary) && (logical AND) | (logical OR) ?: (conditional operator) { }{{ }} (concatenation) Lowest precedence
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
Using Verilog operators listed in Table 8.2 , assume that A=4′b0110, B=4′b0010, and C=4′b0000 and evaluate the result of the following operations:
A * B; A + B; A − B; ∼C; A & B; A B; AΛB; & A; ∼
C; A B;A& & C; A; A < B; A > B; A! = B;

Transcribed Image Text:Table 8.2 Verilog Operator
Precedence
+-!- & -&|- |-1l- (unary)
Highest precedence
*/%
+2 (binary)
VW <<<>>>
<< =>>=
== !==== ! ==
& (binary) (Bitwise, Reduction
AND)
M- -A (binary) (Bitwise, Reduction
OR)
| (binary)
&& (logical AND)
| (logical OR)
?: (conditional operator)
{ }{{ }} (concatenation)
Lowest precedence
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