Suppose A = D6 and B = 7C (both in hexadecimal). Show the step by step result multiplying A and B, using the multiplier hardware shown in Fig. 1. Assume A and B are 8-bit unsigned numbers, stored in hexadecimal format. b) What is the RISC-V instruction that gives the lower 32 bits of the above multiplication of signed integers? Name one register where you will be placing the result and fill in all 32 bit
a) Suppose A = D6 and B = 7C (both in hexadecimal). Show the step by step result multiplying
A and B, using the multiplier hardware shown in Fig. 1. Assume A and B are 8-bit unsigned numbers,
stored in hexadecimal format.
b) What is the RISC-V instruction that gives the lower 32 bits of the above multiplication
of signed integers? Name one register where you will be placing the result and fill in all 32 bit
positions for this instruction (write it both in assembly and in machine language).
c) Suppose for an 8-bit number, each step of operation (either addition or shift) takes 2ns. Please
calculate the time necessary to perform a multiply using the approach given in Fig. 1. Assume the
registers have been initialized. In hardware, please note that the shifts of the multiplicand and multiplier
can be done simultaneously.
![Multiplicand
64 bits
64-bit ALU
Product
Shift right
Control
Write
test
129 bits
Fig. 2: Refined HW of Multiplication Algorithm](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fcb0b1214-7492-41e8-a67f-4dd283d58d70%2F1c4c8507-4ea0-4e73-84c2-1253759c4123%2Flwx5txf_processed.png&w=3840&q=75)
![Multiplicand
Shift left
128 bits
Multiplier
128-bit ALU
Shift right
64 bits
Product
Control test
Write
128 bits
Fig. 1: HW of First (naïve) Multiplication Algorithm](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fcb0b1214-7492-41e8-a67f-4dd283d58d70%2F1c4c8507-4ea0-4e73-84c2-1253759c4123%2Ff33k4pg_processed.png&w=3840&q=75)
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