Assembly language is a low-level programming language for a computer or other programmable device specific to a particular computer architecture in contrast to most high-level programming languages, which are generally portable across multiple systems. Assembly language is converted into executable machine code by a utility program referred to as an assembler like NASM, MASM, etc.

Algorithm 

1. We are taking first element of array in A
2. Comparing A with other elements of array, if A is smaller then store that element in A otherwise compare with next element
3. The value of A is the answer

A         Instruction Set Architecture

A.1        Instruction set

We present a list of instructions typical of a RISC (reduced instruction set computer) machine. In data-movement and control instructions, the addresses may be immediate #X, direct (memory) M, indirect (memory) [M], register r, or register indirect [r] addresses. Data-processing instructions use immediate or register addressing. PC is the programme counter and a <- b indicates that the value of b is placed in a.

LOAD a, b                    a <- b

STOR a, b                    a <- b

ADD a, b, c               a <- b + c

ASH a, b, c               a <- (b >>[s] c)

LSH a, b, c               a <- (b >>[u] c) BR a               PC <- a

OR a, b, c                 a <- b | c

NOT a, b                      a <- !b

BLE a, b, c               PC <- a if b <= c BGE a, b, c            PC <- a if b >= c

Note:  Here b >>[s]  c denotes the arithmetical shift of b to the right by c positions, and

b >>[u]  c denotes the logical shift of b to the right by c positions.

A.2       The pipeline

We will use a five-stage pipeline:

• IF (instruction fetch),
• ID (instruction decode),
• RR (register read),
• EX (execute instruction),
• WB (write back result into register).
• Note that for some instructions (e.g., LOAD r, #X) some of the pipeline stages (e.g., RR) are not

A.3       Execution rules

The rules for the execution of instructions are as follows:

1. All instructions go through the IF and ID stages
2. For data-movement instructions the data transfer between the CPU and main mem- ory happens in the execute stage. (This means that if a data transfer operation is executing, no data can be transferred across the main-memory )
3. Immediate addressing for input arguments does not require RR or EX (e.g., LOAD r1, #X).
4. Arithmetic and logic instructions need RR, EX and
5. Branching operations require RR, EX and WB, unless all operands are immediate, in which case only EX and WB are
6. For the instruction LOAD a, b the argument b must be an immediate address or memory location and a must be a
7. For the instruction STOR a, b the argument b must be an immediate address or register and a must be a memory
8. For each of the remaining instructions the arguments a, b and c must all be registers or immediate
9. You may assume for the sake of the questions that the ISA supports floating point arithmetic with no loss of precision