ss bus and multiple blocks of 1MB memory units. It is ory system that maximizes the main memory size but

Computer Networking: A Top-Down Approach (7th Edition)
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ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
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Question 24
Given a CPU with 24-bits address bus and multiple blocks of 1MB memory units. It is
required to design a main memory system that maximizes the main memory size but
without using any extra hardware.
A) What is the maximum blocks of 1MB memory units that can be used?
B) What is the main memory size that can be acheived?
C) What is the memory decoding technique that can be used?
D) Draw the block diagram that shows the system design. In your diagram, show
clearly the connections between the CPU address lines (A23-AO) and the individual
1MB memory blocks.
The system CPU can access the memory by activating M/(IOJ and R/W control
signals.
Address Lines
D7-Do
Address Bus
RW
CPU
D7-Do
IMBRAM
CSI
MIO
RW
Cs2
CS1
Memory Function
Write Operation
Read Operation
Memory Block is not elected
Memory Block is not selected
CS2
R/W
1
1
1
1
X.
X
X
X
Transcribed Image Text:Question 24 Given a CPU with 24-bits address bus and multiple blocks of 1MB memory units. It is required to design a main memory system that maximizes the main memory size but without using any extra hardware. A) What is the maximum blocks of 1MB memory units that can be used? B) What is the main memory size that can be acheived? C) What is the memory decoding technique that can be used? D) Draw the block diagram that shows the system design. In your diagram, show clearly the connections between the CPU address lines (A23-AO) and the individual 1MB memory blocks. The system CPU can access the memory by activating M/(IOJ and R/W control signals. Address Lines D7-Do Address Bus RW CPU D7-Do IMBRAM CSI MIO RW Cs2 CS1 Memory Function Write Operation Read Operation Memory Block is not elected Memory Block is not selected CS2 R/W 1 1 1 1 X. X X X
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