• sizeof (int) = 4. Consider the following matrix transpose routine: The src array starts at address 0 and the dst array starts at address 64 (decimal). • There is a single L1 data cache that is direct-mapped, write- through, write-allocate, with a block size of 16 bytes. 1 typedef int array[4] [4]; • The cache has a total size of 32 data bytes, and the cache is 2 initially empty. 3 void transpose2 (array dst, array src) • Accesses to the src and dst arrays are the only sources of read 4 { and write misses, respectively. 5 int i, j: A. For each row and col, indicate whether the access to src[row][col] and dst [row][col] is a hit (h) or a miss (m). For example, reading src[0] [0] is a miss and writing dst[0] [0] is also a miss. 7 for (i = 0; i < 4; i++) { 8. for (j = 0; j < 4; j++) { dst [j] [i] = src[i][j]; 9 10 dst array sre array 11 Col. 0 Col. 1 Col. 2 Col. 3 Col. 0 Col. 1 Col. 2 Col. 3 12 Row m Row Row Row Assume this code runs on a machine with the following properties: 1 1 Row Row 2 Row Row 3 3
• sizeof (int) = 4. Consider the following matrix transpose routine: The src array starts at address 0 and the dst array starts at address 64 (decimal). • There is a single L1 data cache that is direct-mapped, write- through, write-allocate, with a block size of 16 bytes. 1 typedef int array[4] [4]; • The cache has a total size of 32 data bytes, and the cache is 2 initially empty. 3 void transpose2 (array dst, array src) • Accesses to the src and dst arrays are the only sources of read 4 { and write misses, respectively. 5 int i, j: A. For each row and col, indicate whether the access to src[row][col] and dst [row][col] is a hit (h) or a miss (m). For example, reading src[0] [0] is a miss and writing dst[0] [0] is also a miss. 7 for (i = 0; i < 4; i++) { 8. for (j = 0; j < 4; j++) { dst [j] [i] = src[i][j]; 9 10 dst array sre array 11 Col. 0 Col. 1 Col. 2 Col. 3 Col. 0 Col. 1 Col. 2 Col. 3 12 Row m Row Row Row Assume this code runs on a machine with the following properties: 1 1 Row Row 2 Row Row 3 3
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
Consider the following matrix transpose routine:
1 typedef int array[4][4];
2
3 void transpose2(array dst, array src)
4 {
5 int i, j;
6
7 for (i = 0; i < 4; i++) {
8 for (j = 0; j < 4; j++) {
9 dst[j][i] = src[i][j];
10 }
11 }
12 }
Assume this code runs on a machine with the following properties:
![• sizeof (int) = 4.
Consider the following matrix transpose routine:
The src array starts at address 0 and the dst array starts at
address 64 (decimal).
• There is a single L1 data cache that is direct-mapped, write-
through, write-allocate, with a block size of 16 bytes.
1
typedef int array[4] [4];
• The cache has a total size of 32 data bytes, and the cache is
2
initially empty.
3
void transpose2 (array dst, array src)
• Accesses to the src and dst arrays are the only sources of read
4
{
and write misses, respectively.
5
int i, j:
A. For each row and col, indicate whether the access to
src[row][col] and dst [row][col] is a hit (h) or a miss (m).
For example, reading src[0] [0] is a miss and writing dst[0]
[0] is also a miss.
7
for (i = 0; i < 4; i++) {
8.
for (j = 0; j < 4; j++) {
dst [j] [i] = src[i][j];
9
10
dst array
sre array
11
Col. 0
Col. 1
Col. 2
Col. 3
Col. 0
Col. 1
Col. 2
Col. 3
12
Row
m
Row
Row
Row
Assume this code runs on a machine with the following properties:
1
1
Row
Row
2
Row
Row
3
3](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2Fa3bce4df-4e16-468b-8df3-9b01ee0fdcd8%2F97a82bde-7e61-4057-ab88-ddd170952919%2Fabz8hmu_processed.png&w=3840&q=75)
Transcribed Image Text:• sizeof (int) = 4.
Consider the following matrix transpose routine:
The src array starts at address 0 and the dst array starts at
address 64 (decimal).
• There is a single L1 data cache that is direct-mapped, write-
through, write-allocate, with a block size of 16 bytes.
1
typedef int array[4] [4];
• The cache has a total size of 32 data bytes, and the cache is
2
initially empty.
3
void transpose2 (array dst, array src)
• Accesses to the src and dst arrays are the only sources of read
4
{
and write misses, respectively.
5
int i, j:
A. For each row and col, indicate whether the access to
src[row][col] and dst [row][col] is a hit (h) or a miss (m).
For example, reading src[0] [0] is a miss and writing dst[0]
[0] is also a miss.
7
for (i = 0; i < 4; i++) {
8.
for (j = 0; j < 4; j++) {
dst [j] [i] = src[i][j];
9
10
dst array
sre array
11
Col. 0
Col. 1
Col. 2
Col. 3
Col. 0
Col. 1
Col. 2
Col. 3
12
Row
m
Row
Row
Row
Assume this code runs on a machine with the following properties:
1
1
Row
Row
2
Row
Row
3
3
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