Show the signals (by means of a diagram similar to Fig. 1-7) of theoutputs F and G in Fig. 1-6. Use arbitrary binary signals for theinputs A, B, C, and D.DDy(a) Two-input AND gate (b) Two-input OR gate (c) NOT gate or inverterF-ABCG=A+B+C+DD(d) Three-input AND gate(e) Four-input OR gateFigure 1-6 Symbols for digital logic circuitsXThe input signals x and y in the two-input gates of Fig. 1-6 may exist inone of four possible states: 00, 10, 11, or 01. These input signals areshown in Fig. 1-7, together with the output signals for the AND and ORgates. The timing diagrams of Fig. 1-7 illustrate the response of each circuitsto each of the four possible input binary combinations. The reason for thename inverter for the NOT gate is apparent from a comparison of the signalx (input of inverter) and that of x' (output of inverter).yAND: x yNOT: r'OR: x + y0z=x+y0Bс000010101 10 1000X0Figure 1-7 Input-output signals for gates (a), (b), and (c) of Figure 1-6

Show the signals (by means of a diagram similar to Fig. 1-7) of the outputs F and G in Fig. 1-6. Use arbitrary binary signals for the inputs A, B, C, and D. D" D²=** (a) Two-input AND gate (b) Two-input OR gate (c) NOT gate or inverter F=ABC G=A+B+C+D с D

Show the signals (by means of a diagram similar to Fig. 1-7) of the outputs F and G in Fig. 1-6. Use arbitrary binary signals for the inputs A, B, C, and D. D" D²=** (a) Two-input AND gate (b) Two-input OR gate (c) NOT gate or inverter F=ABC G=A+B+C+D с D

Introductory Circuit Analysis (13th Edition)

13th Edition

ISBN:9780133923605

Author:Robert L. Boylestad

Publisher:Robert L. Boylestad

Chapter1: Introduction

Section: Chapter Questions

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Question

Show the signals (by means of a diagram similar to Fig. 1-7) of the
outputs F and G in Fig. 1-6. Use arbitrary binary signals for the
inputs A, B, C, and D.
D
D
y
(a) Two-input AND gate (b) Two-input OR gate (c) NOT gate or inverter
F-ABC
G=A+B+C+D
D
(d) Three-input AND gate
(e) Four-input OR gate
Figure 1-6 Symbols for digital logic circuits
X
The input signals x and y in the two-input gates of Fig. 1-6 may exist in
one of four possible states: 00, 10, 11, or 01. These input signals are
shown in Fig. 1-7, together with the output signals for the AND and OR
gates. The timing diagrams of Fig. 1-7 illustrate the response of each circuits
to each of the four possible input binary combinations. The reason for the
name inverter for the NOT gate is apparent from a comparison of the signal
x (input of inverter) and that of x' (output of inverter).
y
AND: x y
NOT: r'
OR: x + y
0
z=x+y
0
B
с
0
0
0
0
1
0
1
0
1 1
0 1
0
0
0
X
0
Figure 1-7 Input-output signals for gates (a), (b), and (c) of Figure 1-6

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