Rp Ho Re Vps Vas Figure 7.52 Bi resistance, R

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D 7.103 Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.52. Using a 3-V supply with an
NMOS transistor for which V, = 0.8 V, k, = 4 mA/V², and 2 = 0, provide a design that biases the transistor at Ip =
0.5 mA, with Vps large enough to allow saturation operation for a 1-V negative signal swing at the drain. Use 13
MN as the largest resistor in the feedback-bias network. What values of Rp, RG1, and RG2 have you chosen?
[Hint] Just chose Vos large enough for a 1V signal swing at the drain. To decide Vo, you can first ignore Ig as it's much smaller
than Io; when you get all calculated bias points you can then check to see if your assumption of ignoring Ig is valid or not
Vpp
Rp
Ra
Figure P7.103
Transcribed Image Text:D 7.103 Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.52. Using a 3-V supply with an NMOS transistor for which V, = 0.8 V, k, = 4 mA/V², and 2 = 0, provide a design that biases the transistor at Ip = 0.5 mA, with Vps large enough to allow saturation operation for a 1-V negative signal swing at the drain. Use 13 MN as the largest resistor in the feedback-bias network. What values of Rp, RG1, and RG2 have you chosen? [Hint] Just chose Vos large enough for a 1V signal swing at the drain. To decide Vo, you can first ignore Ig as it's much smaller than Io; when you get all calculated bias points you can then check to see if your assumption of ignoring Ig is valid or not Vpp Rp Ra Figure P7.103
Rp
->
sa
Figure 7.52 Bia
resistance, RG
Transcribed Image Text:Rp -> sa Figure 7.52 Bia resistance, RG
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