Question: Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2. Processor P1 P2 L1 Size 2 KB 4 KB L1 Miss Rate 8% 6% L1 Hit Time 0.66 ns 0.90 ns a) Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates? b) What is the Average Memory Access Time (AMAT) for P1 and P2 (in cycles)?
Question: Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The following table shows data for L1 caches attached to each of two processors, P1 and P2. Processor P1 P2 L1 Size 2 KB 4 KB L1 Miss Rate 8% 6% L1 Hit Time 0.66 ns 0.90 ns a) Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective clock rates? b) What is the Average Memory Access Time (AMAT) for P1 and P2 (in cycles)?
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Hello. Please answer the attached Computer Organization/Design question and its two parts correctly & completely. Please show all of your work for each part.
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Transcribed Image Text:Question:
Assume that main memory accesses take 70 ns and that 36% of all instructions access data memory. The
following table shows data for L1 caches attached to each of two processors, P1 and P2.
Processor
P1
P2
L1 Size
2 KB
4 KB
L1 Miss Rate
8%
6%
L1 Hit Time
0.66 ns
0.90 ns
a) Assuming that the L1 hit time determines the cycle times for P1 and P2, what are their respective
clock rates?
b) What is the Average Memory Access Time (AMAT) for P1 and P2 (in cycles)?
* Please solve both parts correctly. Thank you.
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