Question 5 timescale Ins / 1ps module flipflop (Q, D, clk): input D, clk; output Q; always@ (posedge clk) begin Q<-D; end endmodule Which of the following is true for the above verilog code? Your answer: O A register must be added to the code for the input. O Output is equal to the inverse of the input. O Initial block can also be used instead of always block. O A register must be added to the code for the output. Clear answer Back Next

Question 5 timescale Ins / 1ps module flipflop (Q, D, clk): input D, clk; output Q; always@ (posedge clk) begin Q<-D; end endmodule Which of the following is true for the above verilog code? Your answer: O A register must be added to the code for the input. O Output is equal to the inverse of the input. O Initial block can also be used instead of always block. O A register must be added to the code for the output. Clear answer Back Next

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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