Question 3 We use a 32-bit operating system. Its int types, memory addresses, and registers, such as ESP, EBP and EIP, are represented by 32 bits. We compile a program that calls this function in this operating system. void foo (int **input, int par) { int tag = par; int *arr[10]; printf("%x", tag); if (tag > 1) { while (*input != 0x0000) { *arr = *input; arr++; input++; } } printf(“%x", tag); } (1) Please plot the stack frame of foo function before it returns.
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Please plot the stack frame of foo function before it returns.
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- int i; float x[5], y[5]; [ lots of code deleted... ] for (i=0;i y[i]) x[i] = x[i] + y[i]; [ more code deleted... ] Translate to MIPS assembly language:write assembly x86-64 language File Types c, cpp, and asmCOMPUTER ORGANISATION :: Use RARS simulator to write and execute the two codes below using RISC-V Assembly language.
- Create a program in C++ which simulates a direct cache. The memory array that contains the data to becached is byte addressable and can contain 256 single byte entries or lines. The cache has only 8 entriesor lines. The Data field in each line of the cache is 8 bits. Since the data stored in each line of the cache isonly 8 bits, there is no need for a line field. Only a tag field is needed which is log2(256) = 8 bits.The memory array can be filled with any values of your choice. The program should work by taking userinput of a memory address (index). This input represents the memory data that should be cached.Check the cache to see if the item is already cached. If it is not, your program should counta cache miss, and then replace the item currently in the cache with the data from the inputted address.Allow the user to input addresses (in a loop), until they so choose to end the program. The program should output the number of cache misses upon ending.Create a program in C++ which simulates a direct cache. The memory array that contains the data to be cached is byte addressable and can contain 256 single byte entries or lines. The cache has only 8 entries or lines. The Data field in each line of the cache is 8 bits. Since the data stored in each line of the cache is only 8 bits, there is no need for a line field. Only a tag field is needed which is log2(256) = 8 bits. The memory array can be filled with any values of your choice. The program should work by taking user input of a memory address (index). This input represents the memory data that should be cached. Your program will check the cache to see if the item is already cached. If it is not, your program should count a cache miss, and then replace the item currently in the cache with the data from the inputted address. Allow the user to input addresses (in a loop), until they so choose to end the program. The program should output the number of cache misses upon ending.Write the mnemonics of the following program: The pressure of two boilers is monitored and controlled by a microcomputer works based on microprocessor programming. A set of 6 readings of first boiler, recorded by six pressure sensors, which are stored in the memory location starting from 2050H. A corresponding set of 6 reading from the second boiler is stored at the memory location starting from 2060H. Each reading from the first set is expected to be higher than the corresponding position in the second set of readings. Write an 8085 sequence to check whether the first set of reading is higher than the second one or not. If all the readings of first set is higher than the second set, store 00 in the ‘D’ register. If any one of the readings is lower than the corresponding reading of second set, stop the process and store FF in the register ‘D’. Data (H): First set: 78, 89, 6A, 80, 90, 85 Second Set:71, 78, 65, 89, 56, 75
- Computer scienceCOMPUTER ORGANISATION : Use RARS simulator to write and execute the two codes below using RISC-V Assembly language.Consider the following C code: int A[16]; int B[16]; int m; ... //A large chunk of code that does NOT access //arrays A and B. .. for (int i=0; i<10; i++) { for (int j=0; j<16; j++) { B[j] = m * A[j] + B[j]; } } Assume this program runs on a 32-bit machine, i.e., the CPU loads/stores 4 bytes from memory in one go. This machine has a 16-bit memory address, and each memory block stores 16 bytes. This machine has a direct-mapped data cache with 16 cache lines. Array A starts at address O, and B starts at address 256 - both arrays begin at a memory block boundary. Each element of arrays A and B occupies 4 bytes. The values of i, j, and m are stored in CPU registers. Q5.1 A compulsory cache miss happens the first time the CPU reads any bytes in a memory block. Such cache misses are inevitable, and the entire memory block must be brought into the cache. How many compulsory misses in the data cache will occur when running the above code? Give your answer in a base 10 number (and only write…
- 1. address of Compute the missing addresses based on the execution of the following C code: struct S{ inti1; char c2[2]; double d3; char c4[8]; }; void foo(struct S * p1, int n) { int * p2 = &p1->i1; char * p3 = &p1->c2[4]; struct S* p4 = p1-1; char * p5 = p1->c4; } %3D p1 = 0x2a20 p2 = p3 = p4 = p5 =in c++ 6. Consider a 2D array A[m][m], each element takes 4 bytes of storage. If the base address at A[1][1] is 1500 and the address of A[4][5] is 1608, determine the order of the matrix when it is stored in Column Major Wise.In c++ write an assembler in which it will read a program written in HACK assembly language from an external file and ultimatley translate each line of code into the binary equivalent that can be run on the computer I built so based off the following hdl files Computer below others are in the images. CHIP Computer { IN reset; PARTS: //Read-only memory (ROM) for instruction fetch ROM32K(address=PC,out=instruction); //Central Processing Unit (CPU) for instruction executionCPU(instruction=instruction,reset=reset,inM=outMemo,outM=CPUoutM,writeM=wM,addressM=adM,pc=PC); //Memory for data storage and control logic Memory(in=CPUoutM,load=wM,address=adM,out=outMemo); }