Question 3: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-12 Index 11-6 Offset 5-0
Question 3: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-12 Index 11-6 Offset 5-0
Chapter6: System Integration And Performance
Section: Chapter Questions
Problem 22VE
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Computer Architecture
![Question 3:
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to
access the cache.
Tag
31-12
Index
11-6
a. What is the cache block size (in words)?
b. How many entries (blocks) does the cache have?
c.
Offset
5-0
What is the ratio between total bits required for such a cache implementation over the data
storage bits?](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F05c98c7a-60b8-469c-97f9-5982586038f6%2Fadad0392-b69f-4c9a-acc0-ff49cd769570%2Fnicd93zh_processed.png&w=3840&q=75)
Transcribed Image Text:Question 3:
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to
access the cache.
Tag
31-12
Index
11-6
a. What is the cache block size (in words)?
b. How many entries (blocks) does the cache have?
c.
Offset
5-0
What is the ratio between total bits required for such a cache implementation over the data
storage bits?
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