Question 3: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-12 Index 11-6 Offset 5-0

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
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Computer Architecture

Question 3:
For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to
access the cache.
Tag
31-12
Index
11-6
a. What is the cache block size (in words)?
b. How many entries (blocks) does the cache have?
c.
Offset
5-0
What is the ratio between total bits required for such a cache implementation over the data
storage bits?
Transcribed Image Text:Question 3: For a direct-mapped cache design with a 32-bit address, the following bits of the address are used to access the cache. Tag 31-12 Index 11-6 a. What is the cache block size (in words)? b. How many entries (blocks) does the cache have? c. Offset 5-0 What is the ratio between total bits required for such a cache implementation over the data storage bits?
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