Question 11) Assume there are four threads T1, T2, T3 and T4 with 100 instructions each. The instructions in each thread are dependent on the previous instruction, (for example in thread TI, 12 is dependent on n, 13 on 12.. so on) so that if Il is issued in cycle x, 12 can be issued earliest at cycle x+2. The threads do not have any inter- thread dependency. Assume that each instruction takes one cycle to complete, and that the thread switching overhead is 2 cycles. a) Consider a single cycle MIPS processor with 1 PC and 1 Register File. If there is no interleaving of threads, meaning one thread completes before the start of the next thread, how many cycles are required for the completion of all four threads? b) For the same proocessor configuration, if there is a fine-grained multithreading of 1 instruction, what will be execution time in cycles for completion of all the four threads? Hint: 11 of T1 executes followed by a context switch to execute Il of T2... so on. If I1 of T1 is issued in cycdle 1, the 11 of T2 is issued in cycle 4 c) For the same processor configuration, if there is a coarse-grained multithreading of 10 instructions, how many cycles are required for the completion of all four threads?

Question 11) Assume there are four threads T1, T2, T3 and T4 with 100 instructions each. The instructions in each thread are dependent on the previous instruction, (for example in thread TI, 12 is dependent on n, 13 on 12.. so on) so that if Il is issued in cycle x, 12 can be issued earliest at cycle x+2. The threads do not have any inter- thread dependency. Assume that each instruction takes one cycle to complete, and that the thread switching overhead is 2 cycles. a) Consider a single cycle MIPS processor with 1 PC and 1 Register File. If there is no interleaving of threads, meaning one thread completes before the start of the next thread, how many cycles are required for the completion of all four threads? b) For the same proocessor configuration, if there is a fine-grained multithreading of 1 instruction, what will be execution time in cycles for completion of all the four threads? Hint: 11 of T1 executes followed by a context switch to execute Il of T2... so on. If I1 of T1 is issued in cycdle 1, the 11 of T2 is issued in cycle 4 c) For the same processor configuration, if there is a coarse-grained multithreading of 10 instructions, how many cycles are required for the completion of all four threads?

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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