QI 126 (a) What is the largest address value? (b) List the ports of the memory and tell me how many bits each of them are. (c) Every memory has an embedded Mux N to I in it. What is N in our case? (d) Every menory has an embedded Decoder I to J in it What is I and J in our case? Should the Decoder have an Enable input or Not, and why? (e) If I implented this memory with flops, how many would I need? () Implementing a memory directly with transistors instead of flops and gates improves which of the following: Area, Power, Access Time fgi lf we want to modify this memory to read-only, which pin(s) can we eliminate? EI have a synchronous single-port read write memory. Its total size 750 B. Its wordsize is

QI 126 (a) What is the largest address value? (b) List the ports of the memory and tell me how many bits each of them are. (c) Every memory has an embedded Mux N to I in it. What is N in our case? (d) Every menory has an embedded Decoder I to J in it What is I and J in our case? Should the Decoder have an Enable input or Not, and why? (e) If I implented this memory with flops, how many would I need? () Implementing a memory directly with transistors instead of flops and gates improves which of the following: Area, Power, Access Time fgi lf we want to modify this memory to read-only, which pin(s) can we eliminate? EI have a synchronous single-port read write memory. Its total size 750 B. Its wordsize is

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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Assume that the base address of the 8255-PPI chip is 0C00H and the address of port C of the chip is 0C04H, which address lines are generating the selection line A1 A0? A. None B. Selection lines A1 A0 from address lines A2 A0 C. Selection lines A1 A0 from address lines A2 A1 D. Selection lines A1 A0 from address lines A3 A2 E. Selection lines A1 A0 from address lines A1 A0
3. A particular SDRAM system uses 24-bit addresses. There are 2 ranksin the system and the burst length is 4 words. Calculate the number ofbits that are used for individual words in the burst, the number of bits forthe rank select, and show how the address bits are organized.
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1) given the size of the word accessible main memory is 1KB and the size of the word is 16-byte, the total number of the registers is 64, what is the minimum number of wires of the address bus?
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In a system the contents of PC, Base register, Register R1, and Register R2 has contents 80, 140, 20, and 40, respectively. Content of R2 is used as the displacement value. What is the effective address computed using the Base addressing and the Relative - Base addressing modes, respectively?
6) A DMA controller transfers 32 bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at a rate of 2400 characters per second. Each character is 8 bit length. The CPU is fetching and executing instructions at an average rate of 1 million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
(i) The contents of the following segment registers are as given. CS = 1111H, DS = 3333H, SS = 2526H. IP = 1232H, SP = 1100H, offset in data segment = 0020H. Calculate the corresponding physical addresses for the addressed byte in (a) CS (b) SS and (c) DS. (ii) The content of DS is 345BH. The amount of data that is to be stored in the data segment is 12K bytes. Where in memory, will this segment be located?
if ALE=0, that mean * the numbers on A7-A15 are high order address bus O all other options are false O the processor reset all buses O the numbers on ADO-AD7 are data bus the address & data bus become in tri-state status O all internal parts are reset O ADO-AD7 are address bus
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A 16Kx4 memory uses coincident decoding by splitting the internal decoder into X-selection(Row Address) and Y-selection (Column Address).a. What is the size of each decoder and how many AND gates are required for decoding theaddress?b. Determine the X and Y selection lines that are enabled when the input address has thebinary equivalent of 6000. Express X and Y in binary and their decimal equivalent.