Q2:Complete the design of the JFET amplifier circuit showen in figure to have a voltage gain magnitude of 17.5dB using a relativety high level of gm for this device defined at Veso=Vp4.„Assume a21ORp and find Z4, Z A. +20v RD 0.1 uF HH 01 uF Vy-4, loss 10 mA 6K Ohnm 10MOhm 100mv 40 uF RE

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Q2:Complete the design of the JFET amplifier circuit showen in figure to have a voltage gain
magnitude of 17.5dB using a relativety high level of gm for this device defined at Veso=Vp4 .Assume
Fa210Rp and find Z,, Z, Aj.
+20v
RD
0.1 uF
HH
0.1 UF
1 k Ohn
Vy-4, Ioss10 ma
6K Ohm
100mv
10 MOhm
40 uF
RE
Transcribed Image Text:Q2:Complete the design of the JFET amplifier circuit showen in figure to have a voltage gain magnitude of 17.5dB using a relativety high level of gm for this device defined at Veso=Vp4 .Assume Fa210Rp and find Z,, Z, Aj. +20v RD 0.1 uF HH 0.1 UF 1 k Ohn Vy-4, Ioss10 ma 6K Ohm 100mv 10 MOhm 40 uF RE
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