Q2(b) illustrates the electrical network with passive components. The Vi and Vo are the input and output voltage, respectively. i) Derive the transfer function, G(s) = Vo(s) / Vi(s) then design the combination of resistor, R2, and capacitor, C, that can produce the step response with an overshoot of 10% and a settling time 1.5 ms. ii) The capacitor is completely discharged before the step input voltage (Vi) of 10 volts is supplied to the system. Formulate the output function of Vo in the time domain. Then plot the unit step response of Vo(t) in a graph (t from 0 s to 3 ms). Indicate the settling time, peak time, and maximum overshoot in the graph.
Q2(b) illustrates the electrical network with passive components. The Vi and Vo are the input and output voltage, respectively. i) Derive the transfer function, G(s) = Vo(s) / Vi(s) then design the combination of resistor, R2, and capacitor, C, that can produce the step response with an overshoot of 10% and a settling time 1.5 ms. ii) The capacitor is completely discharged before the step input voltage (Vi) of 10 volts is supplied to the system. Formulate the output function of Vo in the time domain. Then plot the unit step response of Vo(t) in a graph (t from 0 s to 3 ms). Indicate the settling time, peak time, and maximum overshoot in the graph.
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Fig. Q2(b) illustrates the electrical network with passive components. The Vi and Vo are the input and output voltage, respectively.
i) Derive the transfer function, G(s) = Vo(s) / Vi(s) then design the combination of resistor, R2, and capacitor, C, that can produce the step response with an overshoot of 10% and a settling time 1.5 ms.
ii) The capacitor is completely discharged before the step input voltage (Vi) of 10 volts is supplied to the system. Formulate the output function of Vo in the time domain. Then plot the unit step response of Vo(t) in a graph (t from 0 s to 3 ms). Indicate the settling time, peak time, and maximum overshoot in the graph.
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