Q1: Design a Moore FSM to detect if an input sequence is divisible by 5. Each cycle a new bit comes as input towards LSB (e.g. if the current sequence is '1011' and the input is '0', the new sequence is '10110'). The FSM outputs a logic 1 if the sequence is divisible by 5, otherwise it outputs a logic 0. The starting point for the state diagram and a description of what the state does is depicted below. And assume initially the system is in state S0. a) Draw the Moore state diagram for this FSM using a minimum number of states. b) Draw the excitation table for the states. Define the states in order; e.g. S0 = 000, S1 = 001 etc. c) Write the minimum SOP Expression for all the bits of the states and the output 'O'. I: 0 SO All 0 s1 Remainder 1
Q1: Design a Moore FSM to detect if an input sequence is divisible by 5. Each cycle a new bit comes as input towards LSB (e.g. if the current sequence is '1011' and the input is '0', the new sequence is '10110'). The FSM outputs a logic 1 if the sequence is divisible by 5, otherwise it outputs a logic 0. The starting point for the state diagram and a description of what the state does is depicted below. And assume initially the system is in state S0. a) Draw the Moore state diagram for this FSM using a minimum number of states. b) Draw the excitation table for the states. Define the states in order; e.g. S0 = 000, S1 = 001 etc. c) Write the minimum SOP Expression for all the bits of the states and the output 'O'. I: 0 SO All 0 s1 Remainder 1
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Transcribed Image Text:Q1: Design a Moore FSM to detect if an input sequence is divisible by 5. Each cycle a new bit
comes as input towards LSB (e.g. if the current sequence is '1011' and the input is '0', the new
sequence is '10110'). The FSM outputs a logic 1 if the sequence is divisible by 5, otherwise it
outputs a logic 0. The starting point for the state diagram and a description of what the state
does is depicted below. And assume initially the system is in state S0.
a) Draw the Moore state diagram for this FSM using a minimum number of states.
b) Draw the excitation table for the states. Define the states in order; e.g. S0 = 000, S1 =
001 etc.
c) Write the minimum SOP Expression for all the bits of the states and the output 'O'.
I: 0
so
All 0
S1
Remainder 1
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