Q.65 (i) How many 128x8 RAM chips are required to provide a memory capacity of 2048 bytes. (ii) How many lines of address bus must be used to access 2048 bytes of memory. How many lines of these will be common to each chip? (iii) How many bits must be decoded for chip select? What is the size of decoder?

Introductory Circuit Analysis (13th Edition)
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Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
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Q.65 (i) How many 128×8 RAM chips are required to provide a memory capacity of 2048
bytes.
(ii) How many lines of address bus must be used to access 2048 bytes of memory. How
many lines of these will be common to each chip?
(iii) How many bits must be decoded for chip select? What is the size of decoder?
(8)
Transcribed Image Text:Q.65 (i) How many 128×8 RAM chips are required to provide a memory capacity of 2048 bytes. (ii) How many lines of address bus must be used to access 2048 bytes of memory. How many lines of these will be common to each chip? (iii) How many bits must be decoded for chip select? What is the size of decoder? (8)
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