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Q.1 Mark the following statements as true or false and correct second part if false: 1. If devices A and B request the PCI bus transaction, and the arbiter grand bus to A then to B. The master B will begin transaction immediately when GNT#-B is active. 2. In the interconnection structures, the major input and output interconnection for CPU model is: Read, Write for input and external data for output. 3. The basic functions that a computer can perform: CPU, 1/O, and memory. 4. In 4-way set associative cache memory having 16 K sets, the block No. 363751 mapping in set No. 3303. 5. In the Typical Desktop system bus architecture, the devices: Video, SCSI, FAX, Modem and serial are connected to local bus. 6. The most common replacement algorithms in cache memory: von Neumann and Harvard. 7. The SRAM is more complex construction than DRAM, the circuit diagram of the SRAM is: Aditres ne TramtoE Ground 8. The nonvolatile flash memory is a read mostly memory, using mask write mechanism and electrically crasing a byte level of the data. aad ono chins of EPROM

Q.1 Mark the following statements as true or false and correct second part if false: 1. If devices A and B request the PCI bus transaction, and the arbiter grand bus to A then to B. The master B will begin transaction immediately when GNT#-B is active. 2. In the interconnection structures, the major input and output interconnection for CPU model is: Read, Write for input and external data for output. 3. The basic functions that a computer can perform: CPU, 1/O, and memory. 4. In 4-way set associative cache memory having 16 K sets, the block No. 363751 mapping in set No. 3303. 5. In the Typical Desktop system bus architecture, the devices: Video, SCSI, FAX, Modem and serial are connected to local bus. 6. The most common replacement algorithms in cache memory: von Neumann and Harvard. 7. The SRAM is more complex construction than DRAM, the circuit diagram of the SRAM is: Aditres ne TramtoE Ground 8. The nonvolatile flash memory is a read mostly memory, using mask write mechanism and electrically crasing a byte level of the data. aad ono chins of EPROM

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Q.1 Mark the following statements as true or false and correct second part if false: 1. If devices A and B request the PCI bus transaction, and the arbiter grand bus to A then to B. The master B will begin transaction immediately when GNT#-B is active. 2. In the interconnection structures, the major input and output interconnection for CPU model is: Read, Write for input and external data for output. 3. The basic functions that a computer can perform: CPU, I/O, and memory. 4. In 4-way set associative cache memory having 16 K sets, the block No. 363751 mapping in set No. 3303. 5. In the Typical Desktop system bus architecture, the devices: Video, SCSI, FAX, Modem and serial are connected to local bus. 6. The most common replacement algorithms in cache memory: von Neumann and Harvard. 7. The SRAM is more complex construction than DRAM, the circuit diagram of the SRAM is: Adıtrese larer Tramor Storage apacito 8. The nonvolatile flash memory is a read mostly memory, using mask write mechanism and electrically erasing a byte level of the data. 9. To design 128 Kbyte program memory in 8088 processor system, we on need one chips of EPROM 27256. 10. The DRAM architecture has development to many type of advanced DRAM such as: EPROM, EEPROM, and, Flash memory. 11. To Design 256 KWord program memory in 16-bit processor system, wve on need 4 chips of EPROM 27512. 12. The computer memory organized a memory hierarchy system. The access time, cost, and capacity are increases as closer as to the processor. 13. The modificd Harvard architecture is a hybrid between the Harvard and von Neumann Architectures, 14. The control lines include: bus request and bus grand functions, they indicate to memory read and write. 15. The PCle versions are 1.0, 2.0, 3.0, and 4.0. The Transfer rate per lane is: 2 Gbit/s, 4 Gbit/s, 8 Gbit/s, and 16 Gbit/s respectively. 16. The 8-bit ISA bus, 16-bit ISA bus, Extended ISA (32-bit EISA) bus: operates at and 32MHZ respectively. 17. When I MByte memory system organized based on 2 memory model of 512Kbyte and working in range 00000 - 80000-FFFFFh. 8 MHz, 16MHZ, FFFFFH, for first model working in range: 00000-7FFFFH, and second in range (50 Marks)
Transcribed Image Text:Q.1 Mark the following statements as true or false and correct second part if false: 1. If devices A and B request the PCI bus transaction, and the arbiter grand bus to A then to B. The master B will begin transaction immediately when GNT#-B is active. 2. In the interconnection structures, the major input and output interconnection for CPU model is: Read, Write for input and external data for output. 3. The basic functions that a computer can perform: CPU, I/O, and memory. 4. In 4-way set associative cache memory having 16 K sets, the block No. 363751 mapping in set No. 3303. 5. In the Typical Desktop system bus architecture, the devices: Video, SCSI, FAX, Modem and serial are connected to local bus. 6. The most common replacement algorithms in cache memory: von Neumann and Harvard. 7. The SRAM is more complex construction than DRAM, the circuit diagram of the SRAM is: Adıtrese larer Tramor Storage apacito 8. The nonvolatile flash memory is a read mostly memory, using mask write mechanism and electrically erasing a byte level of the data. 9. To design 128 Kbyte program memory in 8088 processor system, we on need one chips of EPROM 27256. 10. The DRAM architecture has development to many type of advanced DRAM such as: EPROM, EEPROM, and, Flash memory. 11. To Design 256 KWord program memory in 16-bit processor system, wve on need 4 chips of EPROM 27512. 12. The computer memory organized a memory hierarchy system. The access time, cost, and capacity are increases as closer as to the processor. 13. The modificd Harvard architecture is a hybrid between the Harvard and von Neumann Architectures, 14. The control lines include: bus request and bus grand functions, they indicate to memory read and write. 15. The PCle versions are 1.0, 2.0, 3.0, and 4.0. The Transfer rate per lane is: 2 Gbit/s, 4 Gbit/s, 8 Gbit/s, and 16 Gbit/s respectively. 16. The 8-bit ISA bus, 16-bit ISA bus, Extended ISA (32-bit EISA) bus: operates at and 32MHZ respectively. 17. When I MByte memory system organized based on 2 memory model of 512Kbyte and working in range 00000 - 80000-FFFFFh. 8 MHz, 16MHZ, FFFFFH, for first model working in range: 00000-7FFFFH, and second in range (50 Marks)
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