processor's memory hierarchy I

Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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D
Question 20
A processor's memory hierarchy has 3 level caches, followed by the main memory. Below are the
miss ratios and latencies experienced by an application:
L1 miss ratio = 0.6
%3D
L1 hit latency = 4 CPI
L2 miss ratio = 0.4
L2 hit latency = 10 CPI
L3 miss ratio - 0.35
L3 miss latency 300 CPI
L3 hit latency 30 CPI
What would be the effective processor performance (in terms of CPI) for the application?
Transcribed Image Text:D Question 20 A processor's memory hierarchy has 3 level caches, followed by the main memory. Below are the miss ratios and latencies experienced by an application: L1 miss ratio = 0.6 %3D L1 hit latency = 4 CPI L2 miss ratio = 0.4 L2 hit latency = 10 CPI L3 miss ratio - 0.35 L3 miss latency 300 CPI L3 hit latency 30 CPI What would be the effective processor performance (in terms of CPI) for the application?
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