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Problems in this exercise assume that the logic blocks used to implement a processor's datapath (COD Figure 4.23) have the following latencies: Sign HMem/ Register D-Mem File 250ps 150 ps Mux ALU Adder 25 ps 200 ps 150ps extend Control 50ps 50ps 20 ps "Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. "Register setup" is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File. Single Register Register gate Read Setup 5 ps 30ps (a) Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in COD Figure 2.20 (LEGV8 instruction encoding). Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR. (b) What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)? (c) What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (d) What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (e) What is the latency of CBZ? (f) What is the latency of B? (g) What is the latency of an I-type instruction? (h) What is the minimum clock period for this CPU?

Problems in this exercise assume that the logic blocks used to implement a processor's datapath (COD Figure 4.23) have the following latencies: Sign HMem/ Register D-Mem File 250ps 150 ps Mux ALU Adder 25 ps 200 ps 150ps extend Control 50ps 50ps 20 ps "Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. "Register setup" is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File. Single Register Register gate Read Setup 5 ps 30ps (a) Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in COD Figure 2.20 (LEGV8 instruction encoding). Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR. (b) What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)? (c) What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (d) What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (e) What is the latency of CBZ? (f) What is the latency of B? (g) What is the latency of an I-type instruction? (h) What is the minimum clock period for this CPU?

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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Problems in this exercise assume that the logic blocks used to implement a processor's datapath (COD Figure 4.23) have the following latencies: Sign HMem/ Register D-Mem File 250 ps 150 ps Mux ALU Adder 25 ps 200 ps 150ps Single Register Register gate Read Setup 5 ps 30ps extend Control 50 ps 20 ps 50ps "Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. "Register setup" is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File. (a) Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in COD Figure 2.20 (LEGV8 instruction encoding). Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR. (b) What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)? (c) What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (d) What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (e) What is the latency of CBZ? (f) What is the latency of B? (g) What is the latency of an I-type instruction? (h) What is the minimum clock period for this CPU?
Transcribed Image Text:Problems in this exercise assume that the logic blocks used to implement a processor's datapath (COD Figure 4.23) have the following latencies: Sign HMem/ Register D-Mem File 250 ps 150 ps Mux ALU Adder 25 ps 200 ps 150ps Single Register Register gate Read Setup 5 ps 30ps extend Control 50 ps 20 ps 50ps "Register read" is the time needed after the rising clock edge for the new register value to appear on the output. This value applies to the PC only. "Register setup" is the amount of time a register's data input must be stable before the rising edge of the clock. This value applies to both the PC and Register File. (a) Although the control unit as a whole requires 50 ps, it so happens that we can extract the correct value of the Reg2Loc control wire directly from the instruction. Thus, the value of this control wire is available at the same time as the instruction. Explain how we can extract this value directly from the instruction. Hints: Carefully examine the opcodes shown in COD Figure 2.20 (LEGV8 instruction encoding). Also, remember that LSR and LSL do not use the Rm field. Finally, ignore STXR. (b) What is the latency of an R-type instruction (i.e., how long must the clock period be to ensure that this instruction works correctly)? (c) What is the latency of LDUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (d) What is the latency of STUR? (Check your answer carefully. Many students place extra muxes on the critical path.) (e) What is the latency of CBZ? (f) What is the latency of B? (g) What is the latency of an I-type instruction? (h) What is the minimum clock period for this CPU?
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