**Problem #08** The waveforms shown below are inputs to a 4-bit binary counter. The input signals represent the clock, count enable, and asynchronous clear. Develop the output waveform.**Diagram Explanation:**The diagram consists of three waveforms labeled CTEN (Count Enable), CLK (Clock), and CLR (Clear):1. **CTEN (Count Enable):** - The waveform is high initially, then goes low, stays low for a duration, goes high again, and repeats this pattern periodically. 2. **CLK (Clock):** - This is a regular, square wave with a consistent frequency, cycling between high and low states.3. **CLR (Clear):** - The waveform begins low, transitions to high, and then returns to low, repeating periodically.**Circuit Schematic Explanation:**To the right of the waveforms, there is a partial schematic labeled "CTR DIV 16":- **Inputs:** - CTEN, CLK, CLR are connected to the counter circuit. - **Outputs:** - The output is labeled with Q₃, Q₂, Q₁, and Q₀, representing the bits of the binary counter.This setup implies that the 4-bit counter produces an output that changes according to the input waveforms, with an asynchronous clear affecting the count sequence. The task is to analyze the waveform inputs to predict the resulting state changes in the counter's output.

Counter doing counting only when CTEN is high, otherwise it remain to its present state. Clear is asynchronous hence when it is active (its active low), counter clears( 0000) Q0 high : - If CTEN is high, Q1 high : - If CTEN is high and Q0 is high to low Q2 high : If CTEN is high and Q1 is high to low This condition not came for given input signals so it remains low for given inputs. for Q3 high : If CTEN is high and Q2 is high to low This condition not came for given input signals so it remains low for given inputs.Output waveform is shown below