I need help with #6 please **Problem #04**: Construct a timing diagram showing sixteen clock pulses.The diagram depicts a three-stage ripple counter built with JK flip-flops. The inputs are labeled as J and K, with the output of each flip-flop connected to the clock input of the next stage. The clock (CLK) signal drives the first flip-flop.- Flip-flop Stage 1: Inputs - J0, K0; Output - Q0- Flip-flop Stage 2: Inputs - J1, K1; Output - Q1- Flip-flop Stage 3: Inputs - J2, K2; Output - Q2The circuit counts clock pulses and advances the count in a binary fashion.**Problem #05**: For problem #04 assume the propagation delay for each flip-flop is 8 ns. Determine the longest propagation delay, and which count states would experience this delay.The propagation delay accumulates through the stages due to the sequential nature of the ripple counter. For a 3-stage counter, the longest delay occurs when all stages toggle, i.e., transitioning from state `111` to `000`. This involves 3 toggles, resulting in a total delay of \(3 \times 8 \, \text{ns} = 24 \, \text{ns}\).**Problem #06**: If the circuit in problem #04 was a synchronous counter, what would be the longest delay time?In a synchronous counter, all flip-flops receive the clock signal simultaneously. Thus, the longest delay would simply be the propagation delay of one flip-flop, which is 8 ns, since the outputs change concurrently.

Part (6): In the synchronous counter, all the clock inputs of the flip-flops are connected with the same clock pulse. Also, it is seen from the figure, the inputs of the flip-flops are high. The timing-diagrams of all flip-flops will be the same. The timing diagram is shown in the below figure: If the propagation delay of each flip-flop is 8 ns, the propagation delay will be reflected at the output of each flip-flop at the same time. So, the timing diagram of each output will be shifted by 8 ns to the right. Hence, the longest delay time will be 8 ns.