I need help with #5 please **Problem #04** Construct a timing diagram showing sixteen clock pulses.The image displays a schematic with three flip-flops connected in series. Each flip-flop is labeled as follows:- **J0 | K0** with an input clock labeled CLK and an output labeled Q0.- **J1 | K1** with an input and an output labeled Q1.- **J2 | K2** with an output labeled Q2.There is a HIGH signal at the top indicating logic level.**Problem #05** For problem #04, assume the propagation delay for each flip-flop is 8 ns. Determine the longest propagation delay, and which count states would experience this delay.### Diagram Explanation:- The diagram illustrates a series of three JK flip-flops which are typically used for binary counting or for creating counters in digital circuits.- Each flip-flop receives the clock signal and produces an output that feeds into the next flip-flop.- The outputs are labeled sequentially from Q0 to Q2, indicating the binary count progression.- The task involves constructing a timing diagram with 16 clock pulses that detail the state transitions of these outputs over time.- The propagation delay mentioned is the time taken for the output to stabilize after a clock pulse is received. In this context, it affects how quickly each flip-flop responds to the clock signal, possibly leading to cumulative delays across the chain.

Here the circuit is given as Inverted output of the first given as a clock to the next flip flop. here first flip flop will activate when clock signal move from 0 to 1. and other two flip flop will activate when signal moves from 0 to 1. The output response of given sequential circuit will be From the above table we can say that It is MOD 4 counter. Since propagation delay of each flip flop is 8ns. so Total longest propagation tpd=8ns×MOD number=8ns×4=32ns