Problem You are given the following Digital circuit. out4 CLK CLK CLK X X out2 CLK (Ctrl) out2 DO x O out4 1. Complete the timing diagram for the circuit until the arrow: CLK X D 2. Assuming X = 1 for the entire operation, construct a transition table for the circuit. Hint: Look at the flip-flop transition tables in the slide deck. What columns are included? 3. For statements 3.1 and 3.2, choose the correct descriptors among the choices given and explain the basis of your answer.¹ 3.1: The circuit is a (positive/negative) (level/edge)-triggered (D/T/SR/JK) flip-flop. 3.2: Input X is a (low/high)-asserted (synchronous/asynchronous) (set/reset) signal. O X

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