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Pipelining in 8086 processors is achieved using which of the following option: O a. By using the counting register CX that acts as counter for LOOP instruction. O b. By using the adder of the Bus Interface Unit that converts logical address to physical address. O.By using accumulator AX, that stores the result of multiplication operation. O d. By using the 6-byte instruction queue that stores pre-fetched instructions while one instruction is being executed.

Pipelining in 8086 processors is achieved using which of the following option: O a. By using the counting register CX that acts as counter for LOOP instruction. O b. By using the adder of the Bus Interface Unit that converts logical address to physical address. O.By using accumulator AX, that stores the result of multiplication operation. O d. By using the 6-byte instruction queue that stores pre-fetched instructions while one instruction is being executed.

Database System Concepts
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Pipelining in 8086 processors is achieved using which of the following option: a. By using the counting register CX that acts as counter for LOOP instruction. O b. By using the adder of the Bus Interface Unit that converts logical address to physical address. O c. By using accumulator AX, that stores the result of multiplication operation. O d. By using the 6-byte instruction queue that stores pre-fetched instructions while one instruction is being executed.
Transcribed Image Text:Pipelining in 8086 processors is achieved using which of the following option: a. By using the counting register CX that acts as counter for LOOP instruction. O b. By using the adder of the Bus Interface Unit that converts logical address to physical address. O c. By using accumulator AX, that stores the result of multiplication operation. O d. By using the 6-byte instruction queue that stores pre-fetched instructions while one instruction is being executed.
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