P/ check register AX if it has two consecutive ones, if so put 1 in BX else puto.
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- CHATER VE Basic Conpuser Orgniation and Dnign Modify the circuit such that the control signals are: TO: AR <- PC, TR <- PC T1: IR <-MIAR] T2: AR <-IR, TRn <-0 T ARPC T IR-MIARL Te AR-IRO-11) -IR(15) Memery wn Ad AR INN LD Conmon baf. g, h: OUT STD_LOGIC a OR AND f. g. h: IN STD LOGIC a, b, c: OUT STD_LOGIC C NOT(b) To implement a 32-1 Mux using 4-1 Muxes and 2-1 Muxes, we need: Select one: a. Eight 2-1 Muxes in the right stage, two 4-1 Muxes in the middle stage and one 2-1 Mux in the left stage Ob. Eight 4-1 Muxes in the right stage, two 4-1 Muxes in the middle stage and one 2-1 Mux in the left stage C. Eight 4-1 Muxes in the right stage, four 2-1 Muxes in the middle stage and one 4-1 Mux in the left stage O d. Eight 4-1 Muxes in the left stage, two 4-1 Muxes in the middle stage and one 2-1 Mux in the right stage Select the correct answer that corresponds to the decimal value of the following number in fixed-point representation 1100.1001 Select one: O a. 12.125 b. 12.75 C. 12.5625 d. 8.5625 ENDigital Logic Design
- code your Boolean function in HDL And.hdl: /** * And gate: * out = 1 if (a == 1 and b == 1) * 0 otherwise */ CHIP And { IN a, b; OUT out; PARTS: Nand(a=a, b=b, out=nandAB); Not(in=nandAB, out=out); } Mystery.hdl CHIP Mystery { IN a, b, c, d; OUT out; PARTS: } Not.hdl /** * Not gate: * out = not in */ CHIP Not { IN in; OUT out; PARTS: // Put your code here: Nand(a=in, b=in, out=out); } Or.hdl /** * Or gate: out = 1 if {a==1 or b==1}, 0 otherwise */ CHIP Or { IN a, b; OUT out; PARTS: Not (in=a, out=nota); Not (in=b, out=notb); Nand (a=nota, b=notb, out=out); }Computer Science write coder1'• r0' waitr1 waitro 1'• r0 r1• r0' r1 r1 grant1 g1<=1 granto g0<=1 The following entity describes the circuit above: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity arbiter2 is port ( clk : in std_logic ; reset : in std_logic ; r: in std_ logic_vector (1 downto 0) ; g: out std_ logic_vector (1 downto 0) end arbiter2 ; Assume the point of entry on reset is the state waitr1. Write the architecture VHDL for this FSM.