Need help Testh bench code in Verilog module Examen1 #(parameter P = 4) ( input [P:0] e_a, input [P:0] e_b, output reg [P+1:0] vs_a ); always @* begin if (e_a[P] == e_b[P]) begin vs_a[P:0] = e_a[P-1:0] + e_b[P-1:0]; vs_a[P+1] = e_a[P]; end else begin if (e_a[P-1:0] > e_b[P-1:0]) begin vs_a[P:0] = e_a[P-1:0] - e_b[P-1:0]; vs_a[P+1] = e_a[P]; end else begin vs_a[P:0] = e_b[P-1:0] - vs_a[P-1:0]; vs_a[P+1] = e_b[P]; end end end endmodule THIS IS THE TEST BENCH module Examen1_TB; #(parameter P=4); reg [P:0] in_a; reg [P:0] in_b; wire [P+1:0] in_s; Examen1_Ins dut(.e_a(in_a), .e_b(in_b), .vs_a(in_s)); initial begin in_a = 5'b 10101; in_b = 5'b 10100; #17; in_a = 5'b 10011; in_b = 5'b 01010; #17; in_a = 5'b 00001; in_b = 5'b 10001; #17; in_a = 5'b 10110; in_b = 5'b 01101; #17; end endmodule
Need help Testh bench code in Verilog
module Examen1
#(parameter P = 4)
(
input [P:0] e_a,
input [P:0] e_b,
output reg [P+1:0] vs_a
);
always @*
begin
if (e_a[P] == e_b[P])
begin
vs_a[P:0] = e_a[P-1:0] + e_b[P-1:0];
vs_a[P+1] = e_a[P];
end
else
begin
if (e_a[P-1:0] > e_b[P-1:0])
begin
vs_a[P:0] = e_a[P-1:0] - e_b[P-1:0];
vs_a[P+1] = e_a[P];
end
else
begin
vs_a[P:0] = e_b[P-1:0] - vs_a[P-1:0];
vs_a[P+1] = e_b[P];
end
end
end
endmodule
THIS IS THE TEST BENCH
module Examen1_TB;
#(parameter P=4);
reg [P:0] in_a;
reg [P:0] in_b;
wire [P+1:0] in_s;
Examen1_Ins dut(.e_a(in_a), .e_b(in_b), .vs_a(in_s));
initial begin
in_a = 5'b 10101;
in_b = 5'b 10100;
#17;
in_a = 5'b 10011;
in_b = 5'b 01010;
#17;
in_a = 5'b 00001;
in_b = 5'b 10001;
#17;
in_a = 5'b 10110;
in_b = 5'b 01101;
#17;
end
endmodule
IMAGE ERRORS
I don't understand what I'm doing wrong, if you could solve it for me I would appreciate it.
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