mstt ucuoLS, whele synlak consisis of an opcode legislet 10o Two SOLE iegislers. Hist uciois 1equ Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. a) Show the execution sequence of the program using in-order-issue and in-order-execution policy. b) Show the execution sequence of the program using in-order-issue and out-of order-execution policy. Compare run time if the CPU uses 3GHZ clock
mstt ucuoLS, whele synlak consisis of an opcode legislet 10o Two SOLE iegislers. Hist uciois 1equ Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only. a) Show the execution sequence of the program using in-order-issue and in-order-execution policy. b) Show the execution sequence of the program using in-order-issue and out-of order-execution policy. Compare run time if the CPU uses 3GHZ clock
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Point
Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only.
a) Show the execution sequence of the program using in-order-issue and in-order-execution policy.
b) Show the execution sequence of the program using in-order-issue and out-of order-execution policy. Compare run time if the CPU uses 3GHZ clock
Instructions
Comment
LOAD R2, [Ri]
ADD R3, R1, R2
STORE [R5], R3
ADD R1, R6, 16H
FPU
SUB R5, R4, R3
FPU
STORE [R2], RS
AND R4, R2, 15H
OR R3, R1, 25H
LOAD R2, M1
SUB R4, R3, R2
FPU
STORE M2, R4
System
Integer ALU
Write-back
Decode
Fetch
Unit-1
Unit-1
Unit-1
Floating Point
Unit
Decode
Fetch
Write-back
Unit-2
Unit-2
Activate Windov
Unit-2
Integer ALU
Go to Settings to acti](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F55f6d136-5f95-4b82-97ec-6bfa09e78ed8%2Fcf8a6a9b-237e-4997-8698-9cab482e5a10%2Fuz2ydzn_processed.png&w=3840&q=75)
Transcribed Image Text:1.
Consider a program having following sequence of instructions, where the syntax consists of an opcode followed by the destination register followed by one or two source registers. Instructions requiring floating Point
Unit (FPU) are indicated in the comment field. Please note that LOAD, STORE and FPU operations require 4, 4 and 3 clock cycles respectively whereas integer operations require one clock cycle only.
a) Show the execution sequence of the program using in-order-issue and in-order-execution policy.
b) Show the execution sequence of the program using in-order-issue and out-of order-execution policy. Compare run time if the CPU uses 3GHZ clock
Instructions
Comment
LOAD R2, [Ri]
ADD R3, R1, R2
STORE [R5], R3
ADD R1, R6, 16H
FPU
SUB R5, R4, R3
FPU
STORE [R2], RS
AND R4, R2, 15H
OR R3, R1, 25H
LOAD R2, M1
SUB R4, R3, R2
FPU
STORE M2, R4
System
Integer ALU
Write-back
Decode
Fetch
Unit-1
Unit-1
Unit-1
Floating Point
Unit
Decode
Fetch
Write-back
Unit-2
Unit-2
Activate Windov
Unit-2
Integer ALU
Go to Settings to acti
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