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Mnemonic, Operands ADDWF 1, d ANDWF 1, d CLRF f CLAW COMF 1,d DECF f. d DECFSZ 1.d INCF 1, d INCFSZ IORWF 1, d 1, d MOVE f. d MOVWF f NOP ALF 1, d RRF 1, d 1, d SUBWF SWARE 14-Bit Opcode Status Description Cycles MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS 00 0111 dfff reft G.DC.Z 1 00 0101 dEEE EEEE 1 00 0001 left t 1 00 0001 0x** **** 1 00 1 00 0011 00 1 (2) 1 1001 dfffffff EEE EEEE 1011 dffffttt 1010 dffffttt 1111 dfff rett 0100 dfff EEEE Z 00 1000 dtft tett 00 1 (2) 00 1 00 1 1 00 0000 LEEE EEEE 1 00 0000 0xx0 0000 1101 dfff EEEE 1 00 с 1 1100 dfff EEEE с 0010 dfff EEE C,DC.Z 00 1110 JEEE Add Wandf AND W with f Clear Clear W Complement Decrement Decrement f, Skip it 0 Increment f Increment f, Skip it 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from! NNNNN N NN 008

Mnemonic, Operands ADDWF 1, d ANDWF 1, d CLRF f CLAW COMF 1,d DECF f. d DECFSZ 1.d INCF 1, d INCFSZ IORWF 1, d 1, d MOVE f. d MOVWF f NOP ALF 1, d RRF 1, d 1, d SUBWF SWARE 14-Bit Opcode Status Description Cycles MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS 00 0111 dfff reft G.DC.Z 1 00 0101 dEEE EEEE 1 00 0001 left t 1 00 0001 0x** **** 1 00 1 00 0011 00 1 (2) 1 1001 dfffffff EEE EEEE 1011 dffffttt 1010 dffffttt 1111 dfff rett 0100 dfff EEEE Z 00 1000 dtft tett 00 1 (2) 00 1 00 1 1 00 0000 LEEE EEEE 1 00 0000 0xx0 0000 1101 dfff EEEE 1 00 с 1 1100 dfff EEEE с 0010 dfff EEE C,DC.Z 00 1110 JEEE Add Wandf AND W with f Clear Clear W Complement Decrement Decrement f, Skip it 0 Increment f Increment f, Skip it 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from! NNNNN N NN 008

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Mnemonic, Operands 1, d 1, d f 1, d f, d 1, d 1, d 1, d 1, d 1, d f 1, d 1, d 1, d ,d 1, d 1, b 1, b 1, b FORTE TRISE 14-Bit Opcode Description Cycles Status Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS 00 0111 dfff rfff G.DC.Z 00 0101 dfff EEEE 1 00 0001 left teft 0001 0xxx **** 1 00 1 00 1001 dfffffff 1 1 (2) 00 0011 deff EEEE 00 1011 dfff ffff 00 1010 dffftttt 1 1 (2) 00 1111 dfff EEEE 0100 dfff ffff 1 00 1 00 1000 dffftttt 00 0000 IEEE EEEE 1 1 00 0000 0xx0 0000 1 00 1101 dfff ffEE 1100 dffftttt 00 00 0010 dfffffff 1110 dfff ffff 00 00 0110 dfff EEEE BIT-ORIENTED FILE REGISTER OPERATIONS 01 00bb bfft fett 01bb bffftttt 01 1 (2) 01 01 10bb bffftttt 11bb bfff EEEE 1 (2) LITERAL AND CONTROL OPERATIONS 11 111x kkkk kkkk C.DC.Z z 11 1001 kkkk kkkk 2 10 Okkk kkkk kkkk 00 0000 0110 0100 TO.PD 2 10 1kkk kkkk kkkk 1 11 Z 1 1000 kkkk kkkk 00xx kkkk kkkk 00 0000 0000 1001 11 2 2 11 01xx kkkk kkkk 0000 0000 1000 00 00 11 110x kkkk kkkk 0000 0110 0011 TOPD 1 C.DC.Z Z 11 1010 kkkk kkkk R/W-x с Add Wandf AND W with f Clear Clear W Complement ! Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip it 0 Inclusive OR W with f Move ! Move W to f No Operation Rotate Left f through Carry Rotate Right through Carry Subtract W from! Swap nibbles inf Exclusive OR W with f BIt Clear I Bit Set! Bit Test f, Skip if Clear Bit Test f, Skip if Set Add Iteral and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal k Exclusive OR literal with W ADDWF ANDWF CLRF CLAW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP ALF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLAWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 R/W-0 R/W-0 R-1 IRP RP1 RPO TO bit 7 EECON1 REGISTER (ADDRESS 88h) U-0 U-0 U-0 R/W-0 EEIF bit 7 REGISTERS ASSOCIATED WITH PORTA Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 05h PORTA 85h TRIỆU RA4/TOCKI RA3 RA2 RA1 TRISA4 TRISA3 TRISA2 TRISA1 REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 06h RB6 RB5 RB4 R87 RB3 RB2 RB1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 06h R-1 R/W-x PD Z R/W-x R/W-0 WRERR WREN 1 R/W-x DC R/S-0 WR bit 0 R/S-0 RD bit 0 Bit 0 RAD TRISAO File Address 00h 01h 02h 03h 04h 05h 06h 07h och 09h 0Ah OBh och Bit o RBO INT TRISBO NNNNN! N NN 008 с C,DC,Z z Indirect addr. (1) Indirect addr (1) TMRO OPTION REG PCL PCL STATUS FSR STATUS FSR PORTA TRIỆU PURTH TRISE EEDATA EECON EECON2(¹) EEADR PCLATH PCLATH INTCON INTCON Bank 0 Eile Addre 80h 81h 82h 83h 84h 85h 86h 87h 56h 89h 8Ah 88h 8Ch Bank 1
Transcribed Image Text:Mnemonic, Operands 1, d 1, d f 1, d f, d 1, d 1, d 1, d 1, d 1, d f 1, d 1, d 1, d ,d 1, d 1, b 1, b 1, b FORTE TRISE 14-Bit Opcode Description Cycles Status Affected MSb LSb BYTE-ORIENTED FILE REGISTER OPERATIONS 00 0111 dfff rfff G.DC.Z 00 0101 dfff EEEE 1 00 0001 left teft 0001 0xxx **** 1 00 1 00 1001 dfffffff 1 1 (2) 00 0011 deff EEEE 00 1011 dfff ffff 00 1010 dffftttt 1 1 (2) 00 1111 dfff EEEE 0100 dfff ffff 1 00 1 00 1000 dffftttt 00 0000 IEEE EEEE 1 1 00 0000 0xx0 0000 1 00 1101 dfff ffEE 1100 dffftttt 00 00 0010 dfffffff 1110 dfff ffff 00 00 0110 dfff EEEE BIT-ORIENTED FILE REGISTER OPERATIONS 01 00bb bfft fett 01bb bffftttt 01 1 (2) 01 01 10bb bffftttt 11bb bfff EEEE 1 (2) LITERAL AND CONTROL OPERATIONS 11 111x kkkk kkkk C.DC.Z z 11 1001 kkkk kkkk 2 10 Okkk kkkk kkkk 00 0000 0110 0100 TO.PD 2 10 1kkk kkkk kkkk 1 11 Z 1 1000 kkkk kkkk 00xx kkkk kkkk 00 0000 0000 1001 11 2 2 11 01xx kkkk kkkk 0000 0000 1000 00 00 11 110x kkkk kkkk 0000 0110 0011 TOPD 1 C.DC.Z Z 11 1010 kkkk kkkk R/W-x с Add Wandf AND W with f Clear Clear W Complement ! Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip it 0 Inclusive OR W with f Move ! Move W to f No Operation Rotate Left f through Carry Rotate Right through Carry Subtract W from! Swap nibbles inf Exclusive OR W with f BIt Clear I Bit Set! Bit Test f, Skip if Clear Bit Test f, Skip if Set Add Iteral and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal k Exclusive OR literal with W ADDWF ANDWF CLRF CLAW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP ALF RRF SUBWF SWAPF XORWF BCF BSF BTFSC BTFSS ADDLW ANDLW CALL CLAWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 R/W-0 R/W-0 R-1 IRP RP1 RPO TO bit 7 EECON1 REGISTER (ADDRESS 88h) U-0 U-0 U-0 R/W-0 EEIF bit 7 REGISTERS ASSOCIATED WITH PORTA Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 05h PORTA 85h TRIỆU RA4/TOCKI RA3 RA2 RA1 TRISA4 TRISA3 TRISA2 TRISA1 REGISTERS ASSOCIATED WITH PORTB Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 06h RB6 RB5 RB4 R87 RB3 RB2 RB1 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 06h R-1 R/W-x PD Z R/W-x R/W-0 WRERR WREN 1 R/W-x DC R/S-0 WR bit 0 R/S-0 RD bit 0 Bit 0 RAD TRISAO File Address 00h 01h 02h 03h 04h 05h 06h 07h och 09h 0Ah OBh och Bit o RBO INT TRISBO NNNNN! N NN 008 с C,DC,Z z Indirect addr. (1) Indirect addr (1) TMRO OPTION REG PCL PCL STATUS FSR STATUS FSR PORTA TRIỆU PURTH TRISE EEDATA EECON EECON2(¹) EEADR PCLATH PCLATH INTCON INTCON Bank 0 Eile Addre 80h 81h 82h 83h 84h 85h 86h 87h 56h 89h 8Ah 88h 8Ch Bank 1
Write An assembly program to read whatever data in EEPROM memory location (60h) and put it on PORTB as an output. Write an assembly program to set port A as an input
Transcribed Image Text:Write An assembly program to read whatever data in EEPROM memory location (60h) and put it on PORTB as an output. Write an assembly program to set port A as an input
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