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MIPS

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Q7) Consider the MIPS single cycle architecture shown below. It is required to add to the architecture the following modified store word instruction (swm): swm $rs, Immediate #Mem [R[$rs]] =R[$rs]+signe-extend (I[10-0]) Let the instruction format be Field op rs rt rd immediate 10-0 Bits 31-26 25-21 20-16 15-11 Single Cycle Datapath: PC ALUS3 Read Instru- address ction [31-0] Instruction memory Add RegWrite MemWrite Read Read address data Write address Data Write data memory MemRead ALU OMOK 1[25-21] Read Read register 1 data 1 1[20-16] Read register 2 Read Result data 2 115-111 Write register Registers ALUOp2 Write data ALUSro1 ALUS2 [10-0] Sign extend Assume that the delay time for the functional units of this archeticture are as follows: Instruction/data memory access time = 500 ps, Instruction Decode and Register read = 300 ps, Register write = 100 ps, ALU delay = 300 ps. Other elements delay is ignored. What would be the cycle time for execting the above instruction. Result ALUOP1 HERO) MEZO) ALU
Transcribed Image Text:Q7) Consider the MIPS single cycle architecture shown below. It is required to add to the architecture the following modified store word instruction (swm): swm $rs, Immediate #Mem [R[$rs]] =R[$rs]+signe-extend (I[10-0]) Let the instruction format be Field op rs rt rd immediate 10-0 Bits 31-26 25-21 20-16 15-11 Single Cycle Datapath: PC ALUS3 Read Instru- address ction [31-0] Instruction memory Add RegWrite MemWrite Read Read address data Write address Data Write data memory MemRead ALU OMOK 1[25-21] Read Read register 1 data 1 1[20-16] Read register 2 Read Result data 2 115-111 Write register Registers ALUOp2 Write data ALUSro1 ALUS2 [10-0] Sign extend Assume that the delay time for the functional units of this archeticture are as follows: Instruction/data memory access time = 500 ps, Instruction Decode and Register read = 300 ps, Register write = 100 ps, ALU delay = 300 ps. Other elements delay is ignored. What would be the cycle time for execting the above instruction. Result ALUOP1 HERO) MEZO) ALU
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