Meanings of the logic gate symbols used in Figure I are as follows: AND gate NOR gate NAND gate OR gate

Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
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Question
Figure 1 shows a logic circuit that is used as a control system for an electronic device.
The logic circuit has three inputs (X, Y and Z) and one output (F). As shown in Figure 1,
the logic circuit has a feed back line, by which the last output F is fed back and is used as
the current input to the NAND gate. Therefore, the current output F is determined by three
current inputs X, Y and Z and the last output F. In this control system, among three inputs
X, Y and Z, at most only one input can change its value on each clock cycle.
(Feed back line)
Da
Figure 1 The logic circuit
Meanings of the logic gate symbols used in Figure I are as follows:
AND gate
NAND gate
OR gate
NOR gate
Figure 2 shows sample input/output status of the logic circuit. For example, the output F
on the clock cycle c (value 0) is obtained from the inputs X, Y and Z on the clock cycle c
(values 1, 0 and 1 respectively) and the output F at the clock cycle c-1 (value 0).
Transcribed Image Text:Figure 1 shows a logic circuit that is used as a control system for an electronic device. The logic circuit has three inputs (X, Y and Z) and one output (F). As shown in Figure 1, the logic circuit has a feed back line, by which the last output F is fed back and is used as the current input to the NAND gate. Therefore, the current output F is determined by three current inputs X, Y and Z and the last output F. In this control system, among three inputs X, Y and Z, at most only one input can change its value on each clock cycle. (Feed back line) Da Figure 1 The logic circuit Meanings of the logic gate symbols used in Figure I are as follows: AND gate NAND gate OR gate NOR gate Figure 2 shows sample input/output status of the logic circuit. For example, the output F on the clock cycle c (value 0) is obtained from the inputs X, Y and Z on the clock cycle c (values 1, 0 and 1 respectively) and the output F at the clock cycle c-1 (value 0).
Subquestion 2
From the answer group below, select the correct answer to be inserted into the blank
in the following description.
When the value 1 is obtained on the clock cycle c at the intermediate point T in Figure 1, it
is always true that D
Answer group
a) the output F on the clock cycle c-1 was 0
b) the output F on the clock cycle c-1 was 1
c) both of inputs X and Y on the clock cycle c are 0
d) both of inputs X and Y on the clock cycle c are 1
Transcribed Image Text:Subquestion 2 From the answer group below, select the correct answer to be inserted into the blank in the following description. When the value 1 is obtained on the clock cycle c at the intermediate point T in Figure 1, it is always true that D Answer group a) the output F on the clock cycle c-1 was 0 b) the output F on the clock cycle c-1 was 1 c) both of inputs X and Y on the clock cycle c are 0 d) both of inputs X and Y on the clock cycle c are 1
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