Let's assume that we have 8 bits of data (Argument Register), the first 4 bits of which are addresses and the last 4 bits are data bits. You are asked to design a system that transfers this data to the system in parallel with a single clock pulse and makes comparison using address bits. Use the Key register for this comparison.(Elimizde ilk 4 biti adres, son 4 biti data biti olan 8 bitlik bir verimiz olduğunu varsayalım (Argument Register). Bu veriyi sisteme tek bir clock darbesiyle paralel olarak aktaran ve adres bitlerini kullanarak karşılaştırma yapan bir sistem tasarlamanız istenmektedir. Bu karşılaştırma işlemi için Key register kullanınız. )
Let's assume that we have 8 bits of data (Argument Register), the first 4 bits of which are addresses and the last 4 bits are data bits. You are asked to design a system that transfers this data to the system in parallel with a single clock pulse and makes comparison using address bits. Use the Key register for this comparison.(Elimizde ilk 4 biti adres, son 4 biti data biti olan 8 bitlik bir verimiz olduğunu varsayalım (Argument Register). Bu veriyi sisteme tek bir clock darbesiyle paralel olarak aktaran ve adres bitlerini kullanarak karşılaştırma yapan bir sistem tasarlamanız istenmektedir. Bu karşılaştırma işlemi için Key register kullanınız. )
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This question is in the course of computer architecture. I need the answer ASAP. Solving any part of the homework would be greatly appreciated! Thanks! (Ignore the Turkish translations)
![Let's assume that we have 8 bits of data (Argument Register), the first 4 bits of which are addresses and the last 4 bits
are data bits. You are asked to design a system that transfers this data to the system in parallel with a single clock pulse and
makes comparison using address bits. Use the Key register for this comparison.(Elimizde ilk 4 biti adres, son 4 biti data biti
olan 8 bitlik bir verimiz olduğunu varsayalım (Argument Register). Bu veriyi sisteme tek bir clock darbesiyle paralel olarak
aktaran ve adres bitlerini kullanarak karşılaştırma yapan bir sistem tasarlamanız istenmektedir. Bu karşılaştırma işlemi için
Key register kullanınız. )
If the address bit of the data is found in memory, the match bit for the corresponding memory line will be 1. Accordingly,
you are asked to create the system that transfers the match bit "1" value and the data bits of that line to the output using
logic circuit gates. (Eğer verinin adres biti bellekte bulunursa ilgili bellek satırına ait uyuşma biti 1 olacak. Buna göre çıkışa
uyuşma biti "1" değerini ve o satıra ait veri bitlerini aktaran sistemi lojik devre kapıları kullanarak oluşturmanız
istenmektedir. Uyuşma biti ve data biti olmak üzere 5 bitlik bir çıkış beklenmektedir.)
Not: Desired flip-flop type can be used. (İstenilen flip-flop çeşidi kullanılabilir. )](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F133f0168-ee19-4c75-bf31-6fac3d062d62%2F9aba8dc9-dbe1-4695-8b83-4ccb06880e69%2Flg6r3zv_processed.jpeg&w=3840&q=75)
Transcribed Image Text:Let's assume that we have 8 bits of data (Argument Register), the first 4 bits of which are addresses and the last 4 bits
are data bits. You are asked to design a system that transfers this data to the system in parallel with a single clock pulse and
makes comparison using address bits. Use the Key register for this comparison.(Elimizde ilk 4 biti adres, son 4 biti data biti
olan 8 bitlik bir verimiz olduğunu varsayalım (Argument Register). Bu veriyi sisteme tek bir clock darbesiyle paralel olarak
aktaran ve adres bitlerini kullanarak karşılaştırma yapan bir sistem tasarlamanız istenmektedir. Bu karşılaştırma işlemi için
Key register kullanınız. )
If the address bit of the data is found in memory, the match bit for the corresponding memory line will be 1. Accordingly,
you are asked to create the system that transfers the match bit "1" value and the data bits of that line to the output using
logic circuit gates. (Eğer verinin adres biti bellekte bulunursa ilgili bellek satırına ait uyuşma biti 1 olacak. Buna göre çıkışa
uyuşma biti "1" değerini ve o satıra ait veri bitlerini aktaran sistemi lojik devre kapıları kullanarak oluşturmanız
istenmektedir. Uyuşma biti ve data biti olmak üzere 5 bitlik bir çıkış beklenmektedir.)
Not: Desired flip-flop type can be used. (İstenilen flip-flop çeşidi kullanılabilir. )
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