L1 cache requires 5 cycles to access and has a miss rate of 5% L2 cache requires additional 10 cycles to access and has a miss rate of 1% RAM requires additional 110 cycles to access and has a miss rate of 0% Calculate the average memory access time based on the above information. Show the details of your working process.
L1 cache requires 5 cycles to access and has a miss rate of 5% L2 cache requires additional 10 cycles to access and has a miss rate of 1% RAM requires additional 110 cycles to access and has a miss rate of 0% Calculate the average memory access time based on the above information. Show the details of your working process.
Database System Concepts
7th Edition
ISBN:9780078022159
Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan
Chapter1: Introduction
Section: Chapter Questions
Problem 1PE
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L1 cache requires 5 cycles to access and has a miss rate of 5%
L2 cache requires additional 10 cycles to access and has a miss rate of 1%
RAM requires additional 110 cycles to access and has a miss rate of 0%
Calculate the average memory access time based on the above information. Show the details of your working process.
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