iv) Consider the following two diagrams. Left one for memory management unit and right one for the main memory. Suppose Process B is currently executed in CPU and the CPU generates the logical address of 107. What values will be used in the two empty boxes (relocation register and physical address)? Operating System relocation register 14000 304 logical address physical address CPU 416 Process A 346 107 14346 603 Process B MMU 976 1024

iv) Consider the following two diagrams. Left one for memory management unit and right one for the main memory. Suppose Process B is currently executed in CPU and the CPU generates the logical address of 107. What values will be used in the two empty boxes (relocation register and physical address)? Operating System relocation register 14000 304 logical address physical address CPU 416 Process A 346 107 14346 603 Process B MMU 976 1024

Database System Concepts

7th Edition

ISBN:9780078022159

Author:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Publisher:Abraham Silberschatz Professor, Henry F. Korth, S. Sudarshan

Chapter1: Introduction

Section: Chapter Questions

Problem 1PE

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The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=700 W=800 T1=200 T2=200 T3=300
In the following figure, show what happens to the content of memory, ALU registers and the status of the control unit through the 4-phases of executing the instructions M1 to M5. Support program counter is initially holding the address of instruction M1.
Consider a virtual memory system with the following characteristics for accessing memory: 1 nanosecond for a read operation with a hit in cache 5 nanoseconds for a read operation with a miss in cache 2 nanoseconds for a write operation with a hit in cache 10 nanoseconds for a write operation with a miss in cache The cache hit ratio is 0.9 If a sequence of instructions were executed: 100 instruction fetch operations, 60 memory operand read operations, and 40 memory operand write operations, what would be the average memory access time (in nanoseconds) in executing the sequence of instructions:
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1- How to read data from Memory location 0100 by using the figure ? MOV AX,0 0100 0102 0100 Address Bus Data Bus Instruction Pointer Decode Unit General Purpose Register AX Execute Unit Instruction Register a) O MPU generates the address 0100, then the content of 0100 is loaded into Instruction register thru Data bus. b) O Memory informs that it has the instruction address at 0100, then MPU generates this address to access, then instruction is loaded into Instruction register thru Data bus. Accumulator generates the address 0100, then the content of 0100 is loaded into Instruction register thru Data bus. d)O Instruction register generates the instruction address at 0100, then instruction is loaded into Instruction register thru Data bus. C) e) O MPU generates the address 0100 then accesses into Memory thru Data bus. Later on, memory delivers the content of 0100 into Instruction register thru address bus. f)Instruction register generates the address according to Instruction Pointer,…
Suppose that a machine provides instructions that can access memory locations using the one-level indirect addressing scheme. What is the sequence of page faults incurred when all of the pages of a program are currently non-resident and the first instruction of the program is an indirect memory load operation? What happens when the operating system is using a per-process frame allocation technique and only two pages are allocated to this process?
The following diagram shows some registers like processor registers R1 and R2, Program counter PC and Index Register XR along with their corresponding values. It also shows a memory with some instructions like instruction A and next instruction. The memory holds instruction B which consists of four fields as given above. First field of instruction represents the addressing Mode (I), second field specifies Opcode (operation code) ADD representing operation addition, the third field represents Address field 1 and the fourth field represents Address field 2. Consider the following addressing modes, evaluate the result of execution of above instruction by giving steps of evaluation for each addressing mode for the scenario given above. Ø Immediate Mode Ø Direct Mode Ø Register Ø Relative Mode Ø Index Mode Choose your own values for variables (v – w), T1, T2. Choose any one of the given value for T3 (200 or 300). V=600 W=770 T1=200 T2=200 T3=300
Suppose two secondary memory processes exist; wait to execute. In view of phase 1, the priority is high and the other priority is lowest. Just one process will simultaneously fit into the main memory. Explain how CPU is running on it? Can you describe the mechanism among all CPU components?
Part 1: Registers of Different Sizes Registers are fast, but small memory locations that are inside of a CPU. They are used for the CPU's internal computations. A modern 32-bit CPU only contains 8 registers that we are capable of manipulating: EAX, EBX, ECX, EDX, EBP, ESP, ESI, and EDI. Each of these is a 32-bit register (meaning they each hold 32 digit binary numbers). There are many situations where we would want to use smaller portions of data than 32 bits. For example, when working with characters we are primarily using byte data, since each character is stored in just a single byte (which you should know is 8 bits). For this purpose, portions of the 32-bit registers can be referenced directly as if they were smaller registers. The register EAX holds 32-bits. The register AX is the bottom half of EAX, holding just 16 bits. The register AL is the bottom half of AX, holding just 8 bits. There is also AH, which is the top half of AX and also holds 8 bits. EBX, ECX, and EDX can also be…
We want to build a word organized main memory of 8 GB for a 32-bit CPU architecture composed of word organized memory modules of 30-bit address and 8-bit data buses each. a) Draw the interface of the main memory by clearly indicating the widths of the buses. b) Howmanymemorymoduleswouldbenecessarytobuildthememorysystem? c) Design the main memory internal organization built out of the above memory modules (use multiplexers and/or decoders as needed) by clearly indicating the widths of the used busses d) CanweusethismemorysystemasRAMfortheCPUinProblem1?Explainyouranswer.
Assume two secondary memory processes exist. In light of phase 1, one priority is higher than the other. Only one process can fit in main memory. How does the CPU work on it? Can you explain the whole CPU mechanism?