LEGEND: a D NAND а out in out NOT Out D-D OR XOR out in[16] Out[16] AND out E NOT16 a[16] out[16] out[16] a[16]| b[16] D NAND16 a[16] b[16] OR16 b[16] AND16 a[16] \ out[16] b[16] D out[16] XOR16 Inputs: Chip name: Add16 a[16], b[16] Outputs: out [16] Function: out = a + b Comment: Integer 2's complement addition. Overflow is neither detected nor handled.

Systems Architecture
7th Edition
ISBN:9781305080195
Author:Stephen D. Burd
Publisher:Stephen D. Burd
Chapter6: System Integration And Performance
Section: Chapter Questions
Problem 19VE
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please help me design/build  a logic gate using any of these preset gates to make Add16 gate as described in the picture please

LEGEND:
a
D
NAND
а
out
in
out
NOT
Out
D-D
OR
XOR
out
in[16]
Out[16]
AND
out
E
NOT16
a[16]
out[16]
out[16]
a[16]|
b[16]
D
NAND16
a[16]
b[16]
OR16
b[16]
AND16
a[16] \
out[16]
b[16]
D
out[16]
XOR16
Transcribed Image Text:LEGEND: a D NAND а out in out NOT Out D-D OR XOR out in[16] Out[16] AND out E NOT16 a[16] out[16] out[16] a[16]| b[16] D NAND16 a[16] b[16] OR16 b[16] AND16 a[16] \ out[16] b[16] D out[16] XOR16
Inputs:
Chip name: Add16
a[16], b[16]
Outputs:
out [16]
Function:
out = a + b
Comment:
Integer 2's complement addition.
Overflow is neither detected nor handled.
Transcribed Image Text:Inputs: Chip name: Add16 a[16], b[16] Outputs: out [16] Function: out = a + b Comment: Integer 2's complement addition. Overflow is neither detected nor handled.
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