Increasing the degree of pipelining reduces the amount of work done at each pipeline step, enabling more instructions to reside on the processor at the same time and individual instructions to finish faster. However, increasing pipelining does not enhance throughput. Justify this using two reasons.

Increasing the degree of pipelining reduces the amount of work done at each pipeline step, enabling more instructions to reside on the processor at the same time and individual instructions to finish faster. However, increasing pipelining does not enhance throughput. Justify this using two reasons.

Systems Architecture

7th Edition

ISBN:9781305080195

Author:Stephen D. Burd

Publisher:Stephen D. Burd

Chapter4: Processor Technology And Architecture

Section: Chapter Questions

Problem 10RQ: How does pipelining improve CPU efficiency? What’s the potential effect on pipelining’s efficiency...

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If a microprocessor has a cycle time of 0.5 nanoseconds, what’s the processor clock rate? If the fetch cycle is 40% of the processor cycle time, what memory access speed is required to implement load operations with zero wait states and load operations with two wait states?
Pipelining is used because it improves instruction throughput, increasing the level of pipelining cuts the amount of work performed at each pipeline stage, allowing more instructions to exist on the processor at the same time and individual instructions to complete at a more rapid rate. However, throughput will not improve as pipelining is increased indefinitely. Give two reasons for this.
True/False Run times of the typical five stages to execute an instruction are as given in some units of time: Instruction Fetch: 10 Instruction Decode: 15 Execute: 30 Memory: 50 Write Back: 20 If this is implemented as a pipelined versus a non-pipelined machine, then depending on the absence of hazards, one could expect the speedup to be about 2.5.
When making changes to optimize part of a processor, it is often the case that speeding up one type of instruction comes at the cost of slowing down something else. For example, if we put in a complicated fast floating point unit, that takes space, and something might have to be moved farther away from the middle to accommodate it, adding an extra cycle in delay to reach that unit. The basic Amdahl?s law equation does not take into account this trade-off. a. If the new fast floating point unit speeds up floating point operations by, on average 2x, and floating operations take 20% of the original program's execution time, what is the overall speedup (ignoring the penalty to any other instructions)? b. Now assume that speeding up the floating point unit slowed down data cache accesses, resulting in a 1.5x (0r 2/3 speedup). Data cache accesses consume 10% of the execution time. What is the overall speedup now? c. After implementing the new floating point operations, what percentage of…
Yes, even if pipeline instructions take a different amount of time to execute at different times. Where can the problems with this situation be found?
A nonpipelined processor takes 15ns for going through the stages to execute an instruction. The stages each take the following delays per stage: 2ns, 3ns, 4ns, 5ns, 1ns. This is then converted into a pipelined machine with the critical stage determining the cycle time. A second nonpipelined processor also takes 15ns to go through the stages to execute the instructions. The stages, in this case, take the following delays: 3ns, 3ns, 3ns, 3ns, and 3ns. This is then converted into a pipelined machine with the critical stage determining the cycle time. Question: Which of the two pipelined machines created (if any) will have a better throughput? Select the best answer. The two pipelined machines will have identical throughputs because the cycle time of their corresponding nonpipelined machines was identical The second pipelined machine created out of the nonpipelined processor with equal stage delays O The throughput of both the pipelined machines will be identical since the nonpipelined…
clock cycle at which the first of the instructions is fetched as clock cycle 1. Assume that if one instruction reads a register during the same clock cycle as another instruction is writing it, the new value will be read. Do not reorder the instructions. Instructions are fetched and executed exactly in the order given below, with the pipeline stalling if necessary.addi $s2, $s2, 1li $s6, 5add $s1, $s2, $s3move $s5, $s6lw $t1, 0($s5)
Explain the term "pipeline interlock" and its relevance in ensuring proper instruction execution.
Compilers and assemblers may be programmed to sequence instructions in assembly language in such a way that a pipeline faces the least amount of risk feasible. This is one of the goals of pipeline design. To reach the highest possible level of productivity, do all assemblers and compilers rearrange instructions written in assembly language in the same way?
Instead of a single-cycle organization, we can use a multi-cycle organization where each instruction takes multiple cycles but one instruction finishes before another is fetched. In this organization, an instruction only goes through stages it actually needs (e.g., ST only takes 4 cycles because it does not need the WB stage). Compare clock cycle times and execution times with singlecycle, multi-cycle, and pipelined organization.
Suppose an instruction takes 6 cycles to execute in an unpipelined CPU: one cycle to fetch the instruction, one cycle to decode the instruction, one cycle to determine the addressing mode of the operands, one cycle to fetch any operands, one cycle to perform the ALU operation, and one cycle to store the result. In a CPU with a 6 stage pipeline, that instruction still takes 6 cycles to execute, so how can we say the pipeline speeds up the execution of the program?
ANSWER THE QUSTIONS THAT IS WRITEN OR ON THE PICTURE PLEASE Question 6: Suppose in a program there are 120 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the speedup of pipeline parallel processing. Question 7: Suppose in a program there are 300 instructions, and 6 stages are required for each instruction to be processed. Time required in each stage is equivalent to 1 ps. Calculate the efficiency of pipeline parallel processing. Question 8: Consider a 5-stage instruction execution in which, Instruction fetch = ALU operation = Data memory access = 250 ps; and Register read = Register write = 200 ps. Find out the speedup factor for pipelined execution.