In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word:                          0000 0000 0000 1100 0001 1011 0000 0000 Assume that data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched. r0 r1 r2 r3 r4 r5 r6 r8 r12 r31 0 197 -2 -35 4 -100 674 -89 222 -16   2.0.1      What are the outputs of the sign-extend and the jump “Shift left 2” unit (near the top of Figure 4.24) for this instruction word?   2.0.2      For the ALU and the two add units, what are their data input values?

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In this exercise we examine in detail how an instruction is executed in a single-cycle datapath. Problems in this exercise refer to a clock cycle in which the processor fetches the following instruction word:

                         0000 0000 0000 1100 0001 1011 0000 0000

Assume that data memory is all zeros and that the processor’s registers have the following values at the beginning of the cycle in which the above instruction word is fetched.

r0

r1

r2

r3

r4

r5

r6

r8

r12

r31

0

197

-2

-35

4

-100

674

-89

222

-16

 

2.0.1      What are the outputs of the sign-extend and the jump “Shift left 2” unit (near the top of Figure 4.24) for this instruction word?

 

2.0.2      For the ALU and the two add units, what are their data input values?

M
Ex.
4
U PC Address
Add
Instruction
memory
IF/D
Instruction
Read
register 1
Read
register 2
Registers
Write
register
Write
data
RegWrite
Instruction
(15-0)
Instruction
(20-16)
Instruction
(15-11)
16
Read
data 1
Read
data 2
Sign-
extend
32
ID/EX
Shift
left 2
ALUSIC
0
AddAdd
result
RegDst
M
ALU
control
0 ALUOP
M
U
Copyright © 2021 Elsevier Inc. All rights reserved
Zero
Add ALU
result
EX/MEM
Branch
Address
Write
data
PCSrc
MemWrite
Data
memory
MemRead
Read
data
MEM/WB
MemtoReg
IMUNO
Transcribed Image Text:M Ex. 4 U PC Address Add Instruction memory IF/D Instruction Read register 1 Read register 2 Registers Write register Write data RegWrite Instruction (15-0) Instruction (20-16) Instruction (15-11) 16 Read data 1 Read data 2 Sign- extend 32 ID/EX Shift left 2 ALUSIC 0 AddAdd result RegDst M ALU control 0 ALUOP M U Copyright © 2021 Elsevier Inc. All rights reserved Zero Add ALU result EX/MEM Branch Address Write data PCSrc MemWrite Data memory MemRead Read data MEM/WB MemtoReg IMUNO
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