ILLUSTRATE A CIRCUIT THAT GENERATES THE TRUTH TABLE BELOW: S2 0 0 0 0 0 0 0 0 1 1 S1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 A 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 0 X 0 1 1 0 1 1 1 0 0 0 0 1 0 1 0 1 1 0 1 1 Hint: This circuit uses S2 and S1 to select one of four possible outputs. You will need to draw a selector and decoder plus the four different logic gates (See lecture 3, slides 11, 12, and 13) 1 1 0 0 0 Hint 2: The first four X values belong to one logic gate (which is it), the second four X values belong to the second logic gate, etc. Tutor hint: Note that S2 and S1 may need to be reversed as decoder inputs.

Introductory Circuit Analysis (13th Edition)
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ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
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ILLUSTRATE A CIRCUIT THAT GENERATES THE TRUTH TABLE BELOW:
S2
0
0
0
0
0
0
0
0
1
1
1
S1
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
A
0
0
1
1
0
0
1
1
0
0
1
B
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
X
0
1
1
1
1
0
1
1
1
0
1
1
Hint: This circuit uses S2 and S1 to select one of four possible outputs. You will need to
draw a selector and decoder plus the four different logic gates (See lecture 3, slides 11, 12,
and 13)
0
1
1
1
0
0
0
0
1
1
0
0
0
Hint 2: The first four X values belong to one logic gate (which is it), the second four X
values belong to the second logic gate, etc.
Tutor hint: Note that S2 and S1 may need to be reversed as decoder inputs.
Transcribed Image Text:ILLUSTRATE A CIRCUIT THAT GENERATES THE TRUTH TABLE BELOW: S2 0 0 0 0 0 0 0 0 1 1 1 S1 0 1 1 1 1 1 0 0 0 1 1 1 1 0 0 0 0 A 0 0 1 1 0 0 1 1 0 0 1 B 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 X 0 1 1 1 1 0 1 1 1 0 1 1 Hint: This circuit uses S2 and S1 to select one of four possible outputs. You will need to draw a selector and decoder plus the four different logic gates (See lecture 3, slides 11, 12, and 13) 0 1 1 1 0 0 0 0 1 1 0 0 0 Hint 2: The first four X values belong to one logic gate (which is it), the second four X values belong to the second logic gate, etc. Tutor hint: Note that S2 and S1 may need to be reversed as decoder inputs.
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