igital desing answer as soon as possible
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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Question
digital desing
answer as soon as possible
![module Circuit1(a, b, f);
input [3:0]a, b;
output [3:0]f;
reg [3:0]f;
integer i;
always@(a or b)
for (.. .)
endmodule
Listing Q2b
module Circuit2(x, y, z);
input [3:0]x, y;
output [3:0]z;
assign ..
endmodule
Listing Q2c](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F0e23377a-b924-45cc-b123-6df0d4a9db42%2F6f71fc32-74bc-405f-8f53-bc7b057aaecb%2F3jnd3l9_processed.png&w=3840&q=75)
Transcribed Image Text:module Circuit1(a, b, f);
input [3:0]a, b;
output [3:0]f;
reg [3:0]f;
integer i;
always@(a or b)
for (.. .)
endmodule
Listing Q2b
module Circuit2(x, y, z);
input [3:0]x, y;
output [3:0]z;
assign ..
endmodule
Listing Q2c
![Q2. The Verilog code in Listing Q2a describes a digital system using hierarchical design
methodology. The submodule for Circuitl and Circuit2 are given in Listing Q2b and
Q2c, respectively. Sketch the block diagram for given digital system by showing the
interconnection between the modules. Label the signals based on the Verilog code.
module CircuitQ2(A, B, Sel, C, Op, F);
input [3:0]A, B, С;
input Sel, Op;
output reg [3:0]F;
wire [3:0]i, j, k;
Circuitl M1(.a(A), .b(B), .f(i));
Circuit2 M2(.z(j), .x(A), .y(B));
assign k = Sel ? i : j;
always@(k or C or Op)
if (Op)
F= k+ C;
else
F =k – C;
endmodule
Listing Q2a](/v2/_next/image?url=https%3A%2F%2Fcontent.bartleby.com%2Fqna-images%2Fquestion%2F0e23377a-b924-45cc-b123-6df0d4a9db42%2F6f71fc32-74bc-405f-8f53-bc7b057aaecb%2Fqfzpy6m_processed.png&w=3840&q=75)
Transcribed Image Text:Q2. The Verilog code in Listing Q2a describes a digital system using hierarchical design
methodology. The submodule for Circuitl and Circuit2 are given in Listing Q2b and
Q2c, respectively. Sketch the block diagram for given digital system by showing the
interconnection between the modules. Label the signals based on the Verilog code.
module CircuitQ2(A, B, Sel, C, Op, F);
input [3:0]A, B, С;
input Sel, Op;
output reg [3:0]F;
wire [3:0]i, j, k;
Circuitl M1(.a(A), .b(B), .f(i));
Circuit2 M2(.z(j), .x(A), .y(B));
assign k = Sel ? i : j;
always@(k or C or Op)
if (Op)
F= k+ C;
else
F =k – C;
endmodule
Listing Q2a
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