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If the input boardClock is connected to PIN N5, find (a) LPM_MODULUS and (b) the minimum width of q[..] LPM_WIDTH. (c) What bit of q[..] you will pick as your 2.5-MHz clock?

If the input boardClock is connected to PIN N5, find (a) LPM_MODULUS and (b) the minimum width of q[..] LPM_WIDTH. (c) What bit of q[..] you will pick as your 2.5-MHz clock?

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
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Now, if the input clock signal is ADC_CLK_10. Then the input clock signal frequency is 10MHZ. The clock used is Then the modulus of counter required to produce 1.25MHZ signal is obtained as, 50MHZ 1. 25MHZ = 10MH2 M M = 10 = 8 1.25 [a] LPM_MODULUS = 8 [b] for 8 modulus counter, the required number of bits is 2³ =8 Hence, LPM_WIDTH = 3 bits i.e, Q[2:0] [c] The MSB of the Q will give 1.25MHZ signal Hence, the output is Q[2]
Transcribed Image Text:Now, if the input clock signal is ADC_CLK_10. Then the input clock signal frequency is 10MHZ. The clock used is Then the modulus of counter required to produce 1.25MHZ signal is obtained as, 50MHZ 1. 25MHZ = 10MH2 M M = 10 = 8 1.25 [a] LPM_MODULUS = 8 [b] for 8 modulus counter, the required number of bits is 2³ =8 Hence, LPM_WIDTH = 3 bits i.e, Q[2:0] [c] The MSB of the Q will give 1.25MHZ signal Hence, the output is Q[2]
Problem #3: The DE10-Lite board has three clocks that can be seen in the table below: Table 3-2 Pin Assignment of Clock Inputs Signal Name ADC CLK_10 FPGA Pin No. Description PIN N5 MAX10_CLK1_50 PIN_P11 MAX10 CLK2_50 PIN_N14 10 MHz clock input for ADC (Bank 3B) 50 MHz clock inputiBank 3B) 50 MHz clock inputiBank 38) VO Standard 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL You need a clock of 2.5 MHz for your circuit, and for that reason you are going to use a Ipm_counter as a frequency divider shown here: Parameter PM SVALUE Value LPM AVALUE LIM MOBULUS LPM DRCTIN LPM WIDTH LPM_PORT UPOOWN LPM_COUNTER ell If the input boardClock is connected to PIN_N5, find (a) LPM_MODULUS and (b) the minimum width of q[..] LPM_WIDTH. (c) What bit of q[..] you will pick as your 2.5-MHz clock?
Transcribed Image Text:Problem #3: The DE10-Lite board has three clocks that can be seen in the table below: Table 3-2 Pin Assignment of Clock Inputs Signal Name ADC CLK_10 FPGA Pin No. Description PIN N5 MAX10_CLK1_50 PIN_P11 MAX10 CLK2_50 PIN_N14 10 MHz clock input for ADC (Bank 3B) 50 MHz clock inputiBank 3B) 50 MHz clock inputiBank 38) VO Standard 3.3-V LVTTL 3.3-V LVTTL 3.3-V LVTTL You need a clock of 2.5 MHz for your circuit, and for that reason you are going to use a Ipm_counter as a frequency divider shown here: Parameter PM SVALUE Value LPM AVALUE LIM MOBULUS LPM DRCTIN LPM WIDTH LPM_PORT UPOOWN LPM_COUNTER ell If the input boardClock is connected to PIN_N5, find (a) LPM_MODULUS and (b) the minimum width of q[..] LPM_WIDTH. (c) What bit of q[..] you will pick as your 2.5-MHz clock?
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