Homework Help is Here – Start Your Trial Now!
Engineering
Electrical Engineering
(i) Below (figure 1) is an example of a VHDL code for a multiplexer. "00000010000001"WHEN "10000",-Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010". "00000010000001"WHEN "10011". "00000011001111"WHEN "10100", "00000011001111"WHEN "10101", "00000011001111"WHEN "10110", "00000011001111"WHEN "10111", "10011110000001"WHEN "11000", "10011110000001"WHEN "11001", --multiplexer.vhd -Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(e1, d3, d2, dl, d0 : IN STD LOGIC: a,b.c,d,e.f.g.h.ij.k.m,n:OUT STD_LOGIC);: END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC VECTOR (13 downto 0); BEGIN input c el & d3 & d2 & d1 & do; WITH input SELECT output ce "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001", "10011110000001"WHEN "00010", "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111". "00000010000001"WHEN "01000", "00000011001111"WHEN "01001". "10011110000001"WHEN "01010", "10011111001111"WHEN "01011", "00000010000001"WHEN "01100", "00000011001111"WHEN "01101", "10011110000001 WHEN "01110", "10011111001111"WHEN "01111",- "10011110000001"WHEN "11010", "10011110000001"WHEN "11011", "10011111001111"WHEN "11100", "10011111001111"WHEN "11101", "10011111001111"WHEN "11110", 10011111001111"WHEN "11111"; -"00000010000001" -00 -"00000011001111"-01 -"10011110000001" -10 --"10011111001111"-11 --Separate the output vector to make individual pin outputs. he output(13); ie output(12): je output(11): kc= output(10); |e output(9): mc= output(8); nc output(7); a<= output(6); be output(5); C= output(4); de output(3): ec output(2): fe output(1): g= output(0); END mult; Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?

(i) Below (figure 1) is an example of a VHDL code for a multiplexer. "00000010000001"WHEN "10000",-Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010". "00000010000001"WHEN "10011". "00000011001111"WHEN "10100", "00000011001111"WHEN "10101", "00000011001111"WHEN "10110", "00000011001111"WHEN "10111", "10011110000001"WHEN "11000", "10011110000001"WHEN "11001", --multiplexer.vhd -Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(e1, d3, d2, dl, d0 : IN STD LOGIC: a,b.c,d,e.f.g.h.ij.k.m,n:OUT STD_LOGIC);: END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC VECTOR (13 downto 0); BEGIN input c el & d3 & d2 & d1 & do; WITH input SELECT output ce "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001", "10011110000001"WHEN "00010", "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111". "00000010000001"WHEN "01000", "00000011001111"WHEN "01001". "10011110000001"WHEN "01010", "10011111001111"WHEN "01011", "00000010000001"WHEN "01100", "00000011001111"WHEN "01101", "10011110000001 WHEN "01110", "10011111001111"WHEN "01111",- "10011110000001"WHEN "11010", "10011110000001"WHEN "11011", "10011111001111"WHEN "11100", "10011111001111"WHEN "11101", "10011111001111"WHEN "11110", 10011111001111"WHEN "11111"; -"00000010000001" -00 -"00000011001111"-01 -"10011110000001" -10 --"10011111001111"-11 --Separate the output vector to make individual pin outputs. he output(13); ie output(12): je output(11): kc= output(10); |e output(9): mc= output(8); nc output(7); a<= output(6); be output(5); C= output(4); de output(3): ec output(2): fe output(1): g= output(0); END mult; Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?

Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
13th Edition
ISBN:9780133923605
Author:Robert L. Boylestad
Publisher:Robert L. Boylestad
Chapter1: Introduction
Section: Chapter Questions
Problem 1P: Visit your local library (at school or home) and describe the extent to which it provides literature...
See similar textbooks
icon
Related questions
Question
(i) Below (figure 1) is an example of a VHDL code for a multiplexer. --multiplexer.vhd --Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(el, d3, d2, d1, d0 : IN STD_LOGIC; a,b.c,d,e,f.g.h.ij.k,lm,n:OUT STD LOGIC); END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC_VECTOR (13 downto 0); BEGIN input ca el & d3 & d2 & d1 & d0; WITH input SELECT "00000010000001"WHEN "10000",--Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010",- "00000010000001"WHEN "10011",- "00000011001111"WHEN "10100" "00000011001111"WHEN "10101 "00000011001111"WHEN "10110" "00000011001111"WHEN "10111" "10011110000001"WHEN "11000" "10011110000001"WHEN "11001" "10011110000001"WHEN "11010, "10011110000001"WHEN "11011" "10011111001111"WHEN "11100" "100111110011i1"WHEN "11101",- "10011111001111"WHEN "11110",-- "10011111001111"WHEN "11111":-. "00000010000001" -00 --"00000011001111"-01 "10011110000001" -10 "10011111001111" -11 --Separate the output vector to make individual pin outputs. h<= output(13); ice output(12); j<« output(11): kc- output(10); |<e output(9); mc= output(8); nc output(7); a c= output(6): b<= output(5); C= output(4); dc output(3); ec= output(2); fe output(1); g<= output(0); END mult: output c "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001",-- "10011110000001"WHEN "00010",- "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111", "00000010000001"WHEN "01000", "00000011001111"WHEN "01001 "10011110000001"WHEN "01010", "10011111001111"WHEN "01011". "00000010000001"WHEN "01100", "00000011001111"WHEN "01101",- "10011110000001" WHEN "01110",- "100111110011l1"WHEN "01111",-- Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?
Transcribed Image Text:(i) Below (figure 1) is an example of a VHDL code for a multiplexer. --multiplexer.vhd --Common Multiplexer LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY multiplexer IS PORT(el, d3, d2, d1, d0 : IN STD_LOGIC; a,b.c,d,e,f.g.h.ij.k,lm,n:OUT STD LOGIC); END multiplexer; ARCHITECTURE mult OF multiplexer IS SIGNAL input : STD LOGIC_VECTOR (4 downto 0); SIGNAL output : STD LOGIC_VECTOR (13 downto 0); BEGIN input ca el & d3 & d2 & d1 & d0; WITH input SELECT "00000010000001"WHEN "10000",--Input A "00000010000001"WHEN "10001",- "00000010000001"WHEN "10010",- "00000010000001"WHEN "10011",- "00000011001111"WHEN "10100" "00000011001111"WHEN "10101 "00000011001111"WHEN "10110" "00000011001111"WHEN "10111" "10011110000001"WHEN "11000" "10011110000001"WHEN "11001" "10011110000001"WHEN "11010, "10011110000001"WHEN "11011" "10011111001111"WHEN "11100" "100111110011i1"WHEN "11101",- "10011111001111"WHEN "11110",-- "10011111001111"WHEN "11111":-. "00000010000001" -00 --"00000011001111"-01 "10011110000001" -10 "10011111001111" -11 --Separate the output vector to make individual pin outputs. h<= output(13); ice output(12); j<« output(11): kc- output(10); |<e output(9); mc= output(8); nc output(7); a c= output(6): b<= output(5); C= output(4); dc output(3); ec= output(2); fe output(1); g<= output(0); END mult: output c "00000010000001"WHEN "00000",--Input B "00000011001111"WHEN "00001",-- "10011110000001"WHEN "00010",- "10011111001111"WHEN "00011", "00000010000001"WHEN "00100", "00000011001111"WHEN "00101", "10011110000001"WHEN "00110", "10011111001111"WHEN "00111", "00000010000001"WHEN "01000", "00000011001111"WHEN "01001 "10011110000001"WHEN "01010", "10011111001111"WHEN "01011". "00000010000001"WHEN "01100", "00000011001111"WHEN "01101",- "10011110000001" WHEN "01110",- "100111110011l1"WHEN "01111",-- Figure 1 (a) How many bits of input(s) and output(s) are declared in this code? Which line of code supports your answer?
Expert Solution
steps

Step by step

Solved in 2 steps

SEE SOLUTIONCheck out a sample Q&A here
Blurred answer
Knowledge Booster
Multistage amplifier
Learn more about
Need a deep-dive on the concept behind this application? Look no further. Learn more about this topic, electrical-engineering and related others by exploring similar questions and additional content below.
Similar questions
Recommended textbooks for you
Introductory Circuit Analysis (13th Edition)
Introductory Circuit Analysis (13th Edition)
Electrical Engineering
ISBN:
9780133923605
Author:
Robert L. Boylestad
Publisher:
PEARSON
Delmar's Standard Textbook Of Electricity
Delmar's Standard Textbook Of Electricity
Electrical Engineering
ISBN:
9781337900348
Author:
Stephen L. Herman
Publisher:
Cengage Learning
Programmable Logic Controllers
Programmable Logic Controllers
Electrical Engineering
ISBN:
9780073373843
Author:
Frank D. Petruzella
Publisher:
McGraw-Hill Education
Fundamentals of Electric Circuits
Fundamentals of Electric Circuits
Electrical Engineering
ISBN:
9780078028229
Author:
Charles K Alexander, Matthew Sadiku
Publisher:
McGraw-Hill Education
Electric Circuits. (11th Edition)
Electric Circuits. (11th Edition)
Electrical Engineering
ISBN:
9780134746968
Author:
James W. Nilsson, Susan Riedel
Publisher:
PEARSON
Engineering Electromagnetics
Engineering Electromagnetics
Electrical Engineering
ISBN:
9780078028151
Author:
Hayt, William H. (william Hart), Jr, BUCK, John A.
Publisher:
Mcgraw-hill Education,
SEE MORE TEXTBOOKS