Select the two lines that have Verilog syntax errors?1 module mymod (output reg m_out,input in_0, in_1, in_2, in_3,input [1:0] select);always (in_0,in_1,in_2,in_3, select)case (select)346.72'b00:m out =in 0;in 1;in 2;in 3;82'b01:m out2'b10:m out%3D102'b11:m out11end12 endmodule1342. How many R registers does the ATmega168 have? (Write the answer as a decimalinteger.)Previous PageNext PagePage 8 of 10

The correct answer is 32 register.

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How many R registers does the ATmega168 have? (Write the answer as a decimal integer.)

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Select the two lines that have Verilog syntax errors?
1 module mymod (
output reg m_out,
input in_0, in_1, in_2, in_3,
input [1:0] select);
always (in_0,in_1,in_2,in_3, select)
case (select)
3
4
6.
7
2'b00:
m out =
in 0;
in 1;
in 2;
in 3;
8
2'b01:
m out
2'b10:
m out
%3D
10
2'b11:
m out
11
end
12 endmodule
1
3
4
2.

How many R registers does the ATmega168 have? (Write the answer as a decimal
integer.)
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