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How did they get eg pollx and grant-x from REQX?

How did they get eg pollx and grant-x from REQX?

Computer Networking: A Top-Down Approach (7th Edition)
Computer Networking: A Top-Down Approach (7th Edition)
7th Edition
ISBN:9780133594140
Author:James Kurose, Keith Ross
Publisher:James Kurose, Keith Ross
Chapter1: Computer Networks And The Internet
Section: Chapter Questions
Problem R1RQ: What is the difference between a host and an end system? List several different types of end...
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How did they get eg pollx and grant-x from REQX?
library ieee; use ieee.std_logic_1164.all; entity switch is port ( CLK, RESET, REQX, REQY, REQZ : in STD LOGIC; GNTX, GNTY, GNTZ: out STD LOGIC); end switch; architecture behavior of switch is type state is (poll_x, poll_y, poll_z, grant_x, grant_y, grant_z); signal PRESENT_STATE, NEXT_STATE : state; begin process(CLK, RESET) begin if RESET='1' then --asynchronous active HIGH reset PRESENT_STATE <= poll_x; elsif CLK='1' and CLK'event then PRESENT STATE <= NEXT_STATE; end if; end process; process(PRESENT_STATE, REQX, REQY, REQZ) begin GNTX <= '0'; GNTY <= '0'; GNTZ <= '0'; case (PRESENT_STATE) is when poll_x=> if REQX = '1' then NEXT STATE <= grant_x; else NEXT STATE <= poll_y; end if; when poll_y=> if REQY = '1 then NEXT_STATE <= grant_y; else NEXT STATE <= poll_z; end if; when poll_z=> if REQZ = '1' then NEXT STATE <= grant_z; else NEXT_STATE <= poll_x; end if; when grant_x=> GNTX <= '1'; if REQX = '1' then NEXT_STATE <= grant_x; else NEXT_STATE <= poll_y; end if; when grant_y=> GNTY <= '1'; if REQY = '1' then NEXT_STATE <= grant_y; else NEXT STATE <= poll_z; end if; when grant_z=> GNTZ <= '1'; if REQZ = '1' then NEXT_STATE <= grant_z; else NEXT STATE <= poll_x; end if; when others=> NEXT_STATE <= poll_x; end case;
Transcribed Image Text:library ieee; use ieee.std_logic_1164.all; entity switch is port ( CLK, RESET, REQX, REQY, REQZ : in STD LOGIC; GNTX, GNTY, GNTZ: out STD LOGIC); end switch; architecture behavior of switch is type state is (poll_x, poll_y, poll_z, grant_x, grant_y, grant_z); signal PRESENT_STATE, NEXT_STATE : state; begin process(CLK, RESET) begin if RESET='1' then --asynchronous active HIGH reset PRESENT_STATE <= poll_x; elsif CLK='1' and CLK'event then PRESENT STATE <= NEXT_STATE; end if; end process; process(PRESENT_STATE, REQX, REQY, REQZ) begin GNTX <= '0'; GNTY <= '0'; GNTZ <= '0'; case (PRESENT_STATE) is when poll_x=> if REQX = '1' then NEXT STATE <= grant_x; else NEXT STATE <= poll_y; end if; when poll_y=> if REQY = '1 then NEXT_STATE <= grant_y; else NEXT STATE <= poll_z; end if; when poll_z=> if REQZ = '1' then NEXT STATE <= grant_z; else NEXT_STATE <= poll_x; end if; when grant_x=> GNTX <= '1'; if REQX = '1' then NEXT_STATE <= grant_x; else NEXT_STATE <= poll_y; end if; when grant_y=> GNTY <= '1'; if REQY = '1' then NEXT_STATE <= grant_y; else NEXT STATE <= poll_z; end if; when grant_z=> GNTZ <= '1'; if REQZ = '1' then NEXT_STATE <= grant_z; else NEXT STATE <= poll_x; end if; when others=> NEXT_STATE <= poll_x; end case;
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